 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| MVTX2801 Unmanaged 4-Port 1000 Mbps Ethernet Switch Data Sheet Features * 4 Gigabit Ports with GMII and PCS interface * Gigabit Port can also support 100/10 Mbps MII interface February 2003 Ordering Information MVTX2801AG 596-pin HSBGA -40oC to + 85oC WRED mechanism * User controlled thresholds for WRED * * * * High Performance Layer 2 Packet Forwarding (11.904M packets per second) and Filtering at Full-Wire Speed Maximum throughput is 4 Gbps non-blocking Centralized shared-memory architecture Consists of two Memory Domains at 133 MHz * Frame Buffer Domain: one bank of ZBT-SRAM with 1M/2MB total * Switch Database Domain with 256K/512K SRAM. * Classification based on layer 2, 3 markings * VLAN Priority field in VLAN tagged frame. * DS/TOS field in IP packet * The precedence of above two classifications can be programmable * Up to 64K MAC addresses to provide large node aggregation in wiring closet switches * * * * * * Traffic Classification * * * Classify traffic into 8 transmission priorities per port Supports Delay bounded, Strict Priority, and WFQ Provides 2 level dropping precedence with QoS Support Supports IEEE 802.1p/Q Quality of Service with 8 Priority Buffer Management: reserve buffers on per class and per port basis Port-based Priority: VLAN Priority with Tagged frame can be overwritten by the priority of PVID QoS features can be configured on a per port basis Control Full Duplex Ethernet IEEE 802.3x Flow Control Fram e Data Buffer A ZBT-SRAM (1M /2MB) MVTX2801 64bit VTX2800 FDB Interface SRAM 256/512K SW Databasee M AC Table 32bit SDB Interface LED Search Engine NM Database Fram e Engine Scheduler Management Module GMII /PCS Port 0 GMII /PCS Port 1 GMII /PCS Port 2 GMII /PCS Port 3 Serial/ Serial / I2I2C C Figure 1 - Chip Block Diagram i MVTX2801 * * * * * * * * Data Sheet Provides Ethernet Multicast and Broadcast Control 2 Port Trunking groups, max of 3 ports per group (Trunking can be based on source MAC and/or destination MAC and source port) LED signals provided by a serial or parallel interface Synchronous Serial Interface and I2C interface in unmanaged mode. Hardware auto-negotiation through serial management interface (MDIO) for Gigabit Ethernet ports, supports 10/100/1000 Mbps BIST for internal and external SRAM-ZBT I2C EEPROM or synchronous serial port for configuration Packaged in 596-pin BGA Description The MVTX2800 family is a group of 1000 Mbps non-blocking Ethernet switch chips with on-chip address memory. A single chip provides a maximum of eight 1000 Mbps ports and a dedicated CPU interface with a 16/8-bit bus for managed and unmanaged switch applications. The MVTX2800 family consists of the following four products: * * * * MVTX2804 MVTX2803 MVTX2802 MVTX2801 8 8 4 4 Gigabit Gigabit Gigabit Gigabit ports Managed ports Unmanaged ports Managed ports Unmanaged The MVTX2801 supports up to 64K MAC addresses to aggregate traffic from multiple wiring closet stacks. The centralized shared-memory architecture allows a very high performance packet-forwarding rate of 11.904M packet per second at full wire speed. The chip is optimized to provide a low-cost, high performance workgroup, and wiring closet, layer 2 switching solution with 4 Gigabit Ethernet ports. One Frame Buffer Memory domain utilize cost effective, high-performance ZBT-SRAM with aggregated bandwidth of 8.5Gbps to support full wire speed on all external ports simultaneously. With Strict priority, Delay Bounded, and WRR transmission scheduling, plus WRED memory congestion scheme, the chip provides powerful QoS functions for convergent network multimedia and mission-critical applications. The chip provides 8 transmission priorities and 2 level drop precedence. Traffic is assigned its transmission priority and dropping precedence based on the frame VLAN Tag priority. The MVTX2801 supports port trunking/load sharing on the 1000 Mbps ports with fail-over capability. The port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth. In full-duplex mode, IEEE 802.3x flow control is provided. The Physical Coding Sublayer (PCS) is integrated on-chip to provide a direct 10-bit GMII interface, or the PCS can be bypassed to provide an interface to existing fiber-based Gigabit Ethernet transceivers. The MVTX2801 is fabricated using 0.25(m technology. Inputs, however, are 3.3V tolerant and the outputs are capable of directly interfacing to LVTTL levels. The MVTX2801 is packaged in a 596-pin Ball Grid Array package. ii Data Sheet Table of Contents MVTX2801 Features .................................................................................................................................... i Traffic Classification ................................................................................................................ i Description .............................................................................................................................. ii List of Figures ........................................................................................................................ ix List of Tables .......................................................................................................................... xi 1.0 Block Functionality.......................................................................................................... 13 1.1 Frame Data Buffer (FDB) Interfaces ......................................................................................................... 13 1.2 Switch Database (SDB) Interface ............................................................................................................. 13 1.3 GMII/PCS MAC Module (GMAC) .............................................................................................................. 13 1.4 Frame Engine ........................................................................................................................................... 13 1.5 Search Engine .......................................................................................................................................... 13 1.6 LED Interface ............................................................................................................................................ 13 1.7 Internal Memory ........................................................................................................................................ 13 2.0 System Configuration...................................................................................................... 14 2.1 I2C Interface ............................................................................................................................................. 14 2.1.1 Start Condition................................................................................................................................. 14 2.1.2 Address ........................................................................................................................................... 14 2.1.3 Data Direction.................................................................................................................................. 14 2.1.4 Acknowledgment ............................................................................................................................. 14 2.1.5 Data ................................................................................................................................................. 14 2.1.6 Stop Condition ................................................................................................................................. 15 2.2 Synchronous Serial Interface ................................................................................................................... 15 2.2.1 Write Command.............................................................................................................................. 15 2.2.2 Read Command ............................................................................................................................. 16 3.0 Data Forwarding Protocol ............................................................................................... 16 3.1 Unicast Data Frame Forwarding ............................................................................................................... 16 3.2 Multicast Data Frame Forwarding ............................................................................................................. 17 4.0 Memory Interface ............................................................................................................. 17 4.1 Overview ................................................................................................................................................... 17 4.2 Detailed Memory Information .................................................................................................................... 18 5.0 Search Engine .................................................................................................................. 18 5.1 Search Engine Overview........................................................................................................................... 18 5.2 Basic Flow................................................................................................................................................. 18 5.3 Search, Learning, and Aging .................................................................................................................... 19 5.3.1 MAC Search .................................................................................................................................... 19 5.3.2 Learning........................................................................................................................................... 19 5.3.3 Aging ............................................................................................................................................... 19 5.3.4 Data Structure ................................................................................................................................. 19 6.0 Frame Engine ................................................................................................................... 20 6.1 Data Forwarding Summary ....................................................................................................................... 20 6.2 Frame Engine Details................................................................................................................................ 20 6.2.1 FCB Manager ................................................................................................................................. 20 6.2.2 Rx Interface .................................................................................................................................... 20 6.2.3 RxDMA ........................................................................................................................................... 20 6.2.4 TxQ Manager................................................................................................................................... 20 6.3 Port Control ............................................................................................................................................... 21 6.4 TxDMA ...................................................................................................................................................... 21 7.0 Quality of Service and Flow Control .............................................................................. 21 7.1 Model ........................................................................................................................................................ 21 7.2 Four QoS Configurations .......................................................................................................................... 22 7.3 Delay Bound ............................................................................................................................................. 23 iii MVTX2801 Table of Contents Data Sheet 7.4 Strict Priority and Best Effort..................................................................................................................... 23 7.5 Weighted Fair Queuing ............................................................................................................................. 23 7.6 Shaper ...................................................................................................................................................... 24 7.7 WRED Drop Threshold Management Support.......................................................................................... 24 7.8 Buffer Management .................................................................................................................................. 25 7.8.1 Dropping When Buffers Are Scarce ................................................................................................ 26 7.9 Flow Control Basics .................................................................................................................................. 26 7.9.1 Unicast Flow Control ....................................................................................................................... 26 7.9.2 Multicast Flow Control ..................................................................................................................... 26 7.10 Mapping to IETF Diffserv Classes .......................................................................................................... 27 8.0 Port Trunking ................................................................................................................... 28 8.1 Features and Restrictions ......................................................................................................................... 28 8.2 Unicast Packet Forwarding ...................................................................................................................... 28 8.3 Multicast Packet Forwarding.................................................................................................................... 28 8.4 Preventing Multicast Packets from Looping Back to the Source Trunk .................................................... 29 9.0 LED Interface ................................................................................................................... 29 9.1 Introduction ............................................................................................................................................... 29 9.2 Serial Mode............................................................................................................................................... 29 9.3 Parallel Mode ............................................................................................................................................ 30 9.4 LED Control Registers .............................................................................................................................. 30 10.0 Register Definition........................................................................................................ 32 10.1 Register Description................................................................................................................................ 32 10.2 Group 0 Address - MAC Ports Group ..................................................................................................... 35 10.2.1 ECR1Pn: Port N Control Register ................................................................................................. 35 10.2.2 ECR2Pn: Port N Control Register ................................................................................................. 36 10.2.3 GGControl 0- Extra GIGA Port Control ......................................................................................... 37 10.2.4 GGControl 1- Extra GIGA Port Control ......................................................................................... 38 10.3 Group 1 Address - VLAN Group ............................................................................................................. 38 10.3.1 AVTCL - VLAN Type Code Register Low...................................................................................... 38 10.3.2 AVTCH - VLAN Type Code Register High .................................................................................... 39 10.3.3 PVMAP00_0 - Port 00 Configuration Register 0 .......................................................................... 39 10.3.4 P PVMAP00_3 - Port 00 Configuration Register 3........................................................................ 39 10.3.5 PVMODE....................................................................................................................................... 40 10.4 Group 2 Address - Port Trunking Group ................................................................................................. 41 10.4.1 TRUNK0_MODE - Trunk group 0 and 1 mode.............................................................................. 41 10.4.2 TX_AGE - Tx Queue Aging timer .................................................................................................. 41 10.5 Group 4 Address - Search Engine Group ............................................................................................... 42 10.5.1 AGETIME_LOW - MAC address aging time Low.......................................................................... 42 10.5.2 AGETIME_HIGH -MAC address aging time High ......................................................................... 42 10.5.3 SE_OPMODE - Search Engine Operation Mode .......................................................................... 42 10.6 Group 5 Address - Buffer Control/QOS Group ....................................................................................... 43 10.6.1 FCBAT - FCB Aging Timer............................................................................................................ 43 10.6.2 QOSC - QOS Control .................................................................................................................... 43 10.6.3 FCR - Flooding Control Register ................................................................................................... 44 10.6.4 AVPML - VLAN Priority Map ......................................................................................................... 44 10.6.5 AVPMM - VLAN Priority Map ........................................................................................................ 45 10.6.6 AVPMH - VLAN Priority Map......................................................................................................... 45 10.6.7 TOSPML - TOS Priority Map......................................................................................................... 45 10.6.8 TOSPMM - TOS Priority Map........................................................................................................ 46 10.6.9 TOSPMH - TOS Priority Map ........................................................................................................ 46 10.6.10 AVDM - VLAN Discard Map ........................................................................................................ 46 10.6.11 TOSDML - TOS Discard Map...................................................................................................... 47 10.6.12 BMRC - Broadcast/Multicast Rate Control .................................................................................. 47 iv Data Sheet Table of Contents MVTX2801 10.6.13 UCC - Unicast Congestion Control.............................................................................................. 48 10.6.14 MCC - Multicast Congestion Control ........................................................................................... 48 10.6.15 PRG - Port Reservation for Giga ports ........................................................................................ 48 10.6.16 SFCB - Share FCB Size .............................................................................................................. 50 10.6.17 C2RS - Class 2 Reserved Size ................................................................................................... 50 10.6.18 C3RS - Class 3 Reserved Size ................................................................................................... 50 10.6.19 C4RS - Class 4 Reserved Size ................................................................................................... 51 10.6.20 C5RS - Class 5 Reserved Size ................................................................................................... 51 10.6.21 C6RS - Class 6 Reserved Size ................................................................................................... 51 10.6.22 C7RS - Class 7 Reserved Size ................................................................................................... 51 10.6.23 QOSC00 - BYTE_C2_G0 ............................................................................................................ 52 10.6.24 QOSC01 - BYTE_C3_G0 ............................................................................................................ 52 10.6.25 QOSC02 - BYTE_C4_G0 ............................................................................................................ 52 10.6.26 QOSC03 - BYTE_C5_G0 ............................................................................................................ 52 10.6.27 QOSC04 - BYTE_C6_G0 ............................................................................................................ 52 10.6.28 QOSC05 - BYTE_C7_G0 ............................................................................................................ 52 10.6.29 QOSC06 - BYTE_C2_G1 ............................................................................................................ 53 10.6.30 QOSC07 - BYTE_C3_G1 ........................................................................................................... 53 10.6.31 QOSC08 - BYTE_C4_G1 ........................................................................................................... 53 10.6.32 QOSC09 - BYTE_C5_G1 ........................................................................................................... 53 10.6.33 QOSC0A - BYTE_C6_G1........................................................................................................... 53 10.6.34 QOSC0B - BYTE_C7_G1........................................................................................................... 54 10.6.35 QOSC0C - BYTE_C2_G2 .......................................................................................................... 54 10.6.36 QOSC0D - BYTE_C3_G2 .......................................................................................................... 54 10.6.37 QOSC0E - BYTE_C4_G2........................................................................................................... 54 10.6.38 QOSC0F - BYTE_C5_G2........................................................................................................... 54 10.6.39 QOSC10 - BYTE_C6_G2 ............................................................................................................ 55 10.6.40 QOSC11 - BYTE_C7_G2 ............................................................................................................ 55 10.6.41 QOSC12 - BYTE_C2_G3 ........................................................................................................... 55 10.6.42 QOSC13 - BYTE_C3_G3 ............................................................................................................ 55 10.6.43 QOSC14 - BYTE_C4_G3 ............................................................................................................ 55 10.6.44 QOSC15 - BYTE_C5_G3 ............................................................................................................ 55 10.6.45 QOSC16 - BYTE_C6_G3 ........................................................................................................... 56 10.6.46 QOSC17 - BYTE_C7_G3 ............................................................................................................ 56 10.6.47 QOSC33 - CREDIT_C0_G0 ........................................................................................................ 56 10.6.48 QOSC34 - CREDIT_C1_G0 ....................................................................................................... 56 10.6.49 QOSC35 - CREDIT_C2_G0 ........................................................................................................ 57 10.6.50 QOSC36 - CREDIT_C3_G0 ....................................................................................................... 57 10.6.51 QOSC37 - CREDIT_C4_G0 ........................................................................................................ 57 10.6.52 QOSC38 - CREDIT_C5_G0 ........................................................................................................ 57 10.6.53 QOSC39- CREDIT_C6_G0 ......................................................................................................... 58 10.6.54 QOSC3A- CREDIT_C7_G0......................................................................................................... 58 10.6.55 QOSC3B - CREDIT_C0_G1....................................................................................................... 58 10.6.56 QOSC3C - CREDIT_C1_G1 ...................................................................................................... 58 10.6.57 QOSC3D - CREDIT_C2_G1 ....................................................................................................... 59 10.6.58 QOSC3E - CREDIT_C3_G1........................................................................................................ 59 10.6.59 QOSC3F - CREDIT_C4_G1........................................................................................................ 59 10.6.60 QOSC40 - CREDIT_C5_G1 ........................................................................................................ 59 10.6.61 QOSC41- CREDIT_C6_G1 ......................................................................................................... 60 10.6.62 QOSC42- CREDIT_C7_G1 ......................................................................................................... 60 10.6.63 QOSC43 - CREDIT_C0_G2 ....................................................................................................... 60 10.6.64 QOSC44 - CREDIT_C1_G2 ....................................................................................................... 60 10.6.65 QOSC45 - CREDIT_C2_G2 ........................................................................................................ 61 10.6.66 QOSC46 - CREDIT_C3_G2 ....................................................................................................... 61 10.6.67 QOSC47 - CREDIT_C4_G2 ........................................................................................................ 61 v MVTX2801 Table of Contents Data Sheet 10.6.68 QOSC48 - CREDIT_C5_G2....................................................................................................... 61 10.6.69 QOSC49- CREDIT_C6_G2......................................................................................................... 62 10.6.70 QOSC4A- CREDIT_C7_G2 ........................................................................................................ 62 10.6.71 QOSC4B - CREDIT_C0_G3 ...................................................................................................... 62 10.6.72 QOSC4 - CREDIT_C1_G3.......................................................................................................... 63 10.6.73 QOSC4D - CREDIT_C2_G3 ...................................................................................................... 63 10.6.74 QOSC4E - CREDIT_C3_G3 ....................................................................................................... 63 10.6.75 QOSC4F - CREDIT_C4_G3........................................................................................................ 63 10.6.76 QOSC50 - CREDIT_C5_G3........................................................................................................ 64 10.6.77 QOSC51- CREDIT_C6_G3......................................................................................................... 64 10.6.78 QOSC52- CREDIT_C7_G3......................................................................................................... 64 10.6.79 QOSC73 - TOKEN_RATE_G0................................................................................................... 64 10.6.80 QOSC74 - TOKEN_LIMIT_G0 .................................................................................................... 64 10.6.81 QOSC75 - TOKEN_RATE_G1................................................................................................... 65 10.6.82 QOSC76 - TOKEN_LIMIT_G1 .................................................................................................... 65 10.6.83 QOSC77 - TOKEN_RATE_G2.................................................................................................... 65 10.6.84 QOSC78 - TOKEN_LIMIT_G2 .................................................................................................... 65 10.6.85 QOSC79 - TOKEN_RATE_G3................................................................................................... 65 10.6.86 QOSC7A - TOKEN_LIMIT_G3.................................................................................................... 66 10.6.87 RDRC0 - WRED Rate Control 0.................................................................................................. 66 10.6.88 RDRC1 - WRED Rate Control 1.................................................................................................. 66 10.7 Group 6 Address - MISC Group.............................................................................................................. 67 10.7.1 MII_OP0 - MII Register Option 0 .................................................................................................. 67 10.7.2 MII_OP1 - MII Register Option 1 .................................................................................................. 67 10.7.3 FEN - Feature Register ................................................................................................................ 68 10.7.4 MIIC0 - MII Command Register 0.................................................................................................. 68 10.7.5 MIIC1 - MII Command Register 1................................................................................................. 68 10.7.6 MIIC2 - MII Command Register 2................................................................................................. 69 10.7.7 MIIC3 - MII Command Register 3................................................................................................. 69 10.7.8 MIID0 - MII Data Register 0.......................................................................................................... 69 10.7.9 MIID1 - MII Data Register 0........................................................................................................... 69 10.7.10 LED Mode - LED Control............................................................................................................ 70 10.7.11 CHECKSUM - EEPROM Checksum ........................................................................................... 72 10.7.12 LED User..................................................................................................................................... 72 10.7.13 LEDUSER0 ................................................................................................................................. 72 10.7.14 LEDUSER1 ................................................................................................................................ 72 10.7.15 LEDUSER2/LEDSIG2 ................................................................................................................ 73 10.7.16 LEDUSER3/LEDSIG3 ................................................................................................................ 74 10.7.17 LEDUSER4/LEDSIG4 ................................................................................................................. 74 10.7.18 LEDUSER5/LEDSIG5 ................................................................................................................. 75 10.7.19 LEDUSER6/LEDSIG6 ................................................................................................................ 76 10.7.20 LEDUSER7/LEDSIG1_0 ............................................................................................................ 76 10.7.21 MIINP0 - MII Next Page Data Register 0 .................................................................................... 77 10.7.22 MIINP1 - MII Next Page Data Register 1 .................................................................................... 77 10.8 Group F Address - CPU Access Group .................................................................................................. 78 10.8.1 GCR-Global Control Register ........................................................................................................ 78 10.8.2 DCR-Device Status and Signature Register ................................................................................. 78 10.8.3 DCR01-Giga port status ................................................................................................................ 79 10.8.4 DCR23-Giga port status ................................................................................................................ 79 10.8.5 DPST - Device Port Status Register ............................................................................................. 80 10.8.6 DTST - Data Read Back Register ................................................................................................. 80 11.0 BGA and Ball Signal Description ................................................................................ 81 11.1 BGA Views (Top View) .......................................................................................................................... 81 11.2 Power and Ground Distribution.............................................................................................................. 82 vi Data Sheet Table of Contents MVTX2801 11.3 Ball- Signal Descriptions ........................................................................................................................ 83 11.4 Ball Signal Name.................................................................................................................................... 91 11.5 AC/DC Timing ........................................................................................................................................ 97 11.5.1 Absolute Maximum Ratings.......................................................................................................... 97 11.5.2 DC Electrical Characteristics ........................................................................................................ 97 11.5.3 Recommended Operation Conditions .......................................................................................... 97 11.6 Local Frame Buffer ZBT SRAM Memory Interface ................................................................................ 98 11.6.1 Local ZBT SRAM Memory Interface A ......................................................................................... 98 11.7 Local Switch Database SBRAM Memory Interface................................................................................ 99 11.7.1 Local SBRAM Memory Interface .................................................................................................. 99 11.8 AC Characteristics ............................................................................................................................... 100 11.8.1 Media Independent Interface...................................................................................................... 100 11.8.2 Gigabit Media Independent Interface .......................................................................................... 101 11.8.3 PCS Interface ............................................................................................................................. 102 11.8.4 LED Interface.............................................................................................................................. 103 11.8.5 MDIO Input Setup and Hold Timing............................................................................................ 104 11.8.6 I2C Input Setup Timing................................................................................................................ 104 11.8.7 Serial Interface Setup Timing ..................................................................................................... 105 12.0 Mechanical Data..........................................................................................................106 12.1 Packaging Information ......................................................................................................................... 106 vii MVTX2801 Table of Contents Data Sheet viii Data Sheet List of Figures MVTX2801 Figure 1 - Chip Block Diagram.................................................................................................... i Figure 2 - Data Transfer Format for I2C Interface ................................................................... 14 Figure 3 - Write Command ...................................................................................................... 15 Figure 4 - Read Command ...................................................................................................... 16 Figure 5 - SRAM Interface Block Diagram (DMAs for Gigabit Ports)....................................... 17 Figure 6 - Buffer Partition Scheme Used in the MVTX2801 .................................................... 25 Figure 7 - Timing diagram for serial mode in LED interface. ................................................... 29 Figure 8 - Local Memory Interface - Input setup and hold timing............................................. 98 Figure 9 - Local Memory Interface - Output valid delay timing ................................................ 98 Figure 10 - Local Memory Interface - Input setup and hold timing........................................... 99 Figure 11 - Local Memory Interface - Output valid delay timing .............................................. 99 Figure 12 - AC Characteristics - Media Independent Interface.............................................. 100 Figure 13 - AC Characteristics - Media Independent Interface.............................................. 100 Figure 14 - AC Characteristics- GMII..................................................................................... 101 Figure 15 - AC Characteristics - Gigabit Media Independent Interface ................................. 101 Figure 16 - AC Characteristics - PCS Interface ..................................................................... 102 Figure 17 - AC Characteristics - PCS Interface ..................................................................... 102 Figure 18 - AC Characteristics - LED Interface...................................................................... 103 Figure 19 - MDIO Input Setup and Hold Timing .................................................................... 104 Figure 20 - MDIO Output Delay Timing ................................................................................. 104 Figure 21 - I2C Input Setup Timing........................................................................................ 104 Figure 22 - I2C Output Delay Timing ..................................................................................... 105 Figure 23 - Serial Interface Setup Timing .............................................................................. 105 Figure 24 - Serial Interface Output Delay Timing .................................................................. 105 ix MVTX2801 Data Sheet x Data Sheet List of Tables MVTX2801 Table 1 - Two-dimensional World Traffic ................................................................................ 21 Table 2 - Four QoS configurations per port ............................................................................ 22 Table 3 - WRED Dropping Scheme ........................................................................................ 24 Table 4 - Mapping between MVTX2801 and IETF Diffserv Classes for Gigabit Ports............ 27 Table 5 - MVTX2801 Features Enabling IETF Diffserv Standards ......................................... 27 Table 6 - MVTX2801 Register Description ............................................................................. 32 Table 7 - Ball- Signal Descriptions.......................................................................................... 83 Table 8 - Ball Signal Name ..................................................................................................... 91 Table 9 - Recommended Operation Conditions ..................................................................... 97 Table 10 - AC Characteristics - Local frame buffer ZBT-SRAM Memory Interface A ............. 98 Table 11 - AC Characteristics - Local Switch Database SBRAM Memory Interface .............. 99 Table 12 - AC Characteristics - Media Independent Interface .............................................. 100 Table 13 - AC Characteristics - Gigabit Media Independent Interface.................................. 102 Table 14 - AC Characteristics - PCS Interface ..................................................................... 103 Table 15 - AC Characteristics - LED Interface...................................................................... 103 Table 16 - MDIO Timing ....................................................................................................... 104 Table 17 - I2C Timing ........................................................................................................... 105 Table 18 - Serial Interface Timing......................................................................................... 106 xi MVTX2801 Data Sheet xii Data Sheet 1.0 1.1 MVTX2801 Block Functionality Frame Data Buffer (FDB) Interfaces The FDB interface supports pipelined ZBT-SRAM memory at 133 MHz. To ensure a non-blocking switch, one memory domain is required. Each domain has a 64-bit wide memory bus. At 133 MHz, the aggregate memory bandwidth is 8.5 Gbps, which is enough to support 4 Gigabit ports at full wire speed switching. A patent pending scheme is used to access the FDB memory. Each slot has one tick to read or write 8 bytes. 1.2 Switch Database (SDB) Interface A pipelined synchronous burst SRAM (SBRAM) memory is used to store the switch database information including MAC Table. Search Engine accesses the switch database via SDB interface. The SDB bus has 32-bit wide bus at 133MHz. 1.3 GMII/PCS MAC Module (GMAC) The GMII/PCS Media Access Control (MAC) module provides the necessary buffers and control interface between the Frame Engine (FE) and the external physical device (PHY). The MVTX2801 has two interfaces, GMII or PCS. The MAC of the MVTX2801 meets the IEEE 802.3z specification and supports the MII interface. It is able to operate 10M/100M/1G in Full Duplex mode with a back pressure/flow control mechanism. It has the options to insert Source Address/CRC/VLAN ID to each frame. The GMII/PCS Module also supports hot plug detection. 1.4 Frame Engine The main function of the frame engine is to forward a frame to its proper destination port or ports. When a frame arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request, which is sent to the search engine to resolve the destination port. The arriving frame is moved to the FDB. After receiving a switch response from the search engine, the frame engine performs transmission scheduling based on the frame's priority. The frame engine forwards the frame to the MAC module when the frame is ready to be sent. 1.5 Search Engine The Search Engine resolves the frame's destination port or ports according to the destination MAC address (L2) by searching the database. It also performs MAC learning, priority assignment, and trunking functions. 1.6 LED Interface The LED interface can be operated in a serial mode or a parallel mode. In the serial mode, the LED interface uses 3 pins for carrying 4 port status signals. In the parallel mode, the interface can drive LEDs by 8 status pins. The LED port is shared with bootstrap pins. In order to avoid error when reading the bootstraps, a buffer must be used to isolate the LED circuitry from the bootstrap pins during bootstrap cycle (the bootstrap pins are sampled at the rising edge of the Reset). 1.7 Internal Memory Several internal tables are required and are described as follows: * * Frame Control Block (FCB) - Each FCB entry contains the control information of the associated frame stored in the FDB, e.g. frame size, read/write pointer, transmission priority, etc. MCT Link Table - The MCT Link Table stores the linked list of MCT entries that have collisions in the external MAC Table. 13 MVTX2801 2.0 System Configuration Data Sheet The MVTX2801 can be configured by EEPROM (24C02 or compatible) via an I2C interface at boot time, or via a synchronous serial interface during operation. 2.1 I2C Interface The I2C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit serial and bi-directional, at 50 Kbps. Data transfer is performed between master and slave IC using a request / acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer. The figure below shows the data transfer format. SLAVE ADDRESS DATA 1 (8 bits) START R/W ACK ACK DATA 2 ACK DATA M ACK STOP Figure 2 - Data Transfer Format for I2C Interface 2.1.1 Start Condition Generated by the master, the MVTX2801. The bus is considered to be busy after the Start condition is generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line. Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I2C bus is free, both lines are High. 2.1.2 Address The first byte after the Start condition determines which slave the master will select. The slave in our case is the EEPROM. The first seven bits of the first data byte make up the slave address. 2.1.3 Data Direction The eighth bit in the first byte after the Start condition determines the direction (R/W) of the message. A master transmitter sets this bit to W; a master receiver sets this bit to R. 2.1.4 Acknowledgment Like all clock pulses, the master generates the acknowledgment-related clock pulse. However, the transmitter releases the SDA line (High) during the acknowledgment clock pulse. Furthermore, the receiver must pull down the SDA line during the acknowledge pulse so that it remains stable Low during the High period of this clock pulse. An acknowledgment pulse follows every byte transfer. If a slave receiver does not acknowledge after any byte, then the master generates a Stop condition and aborts the transfer. If a master receiver does not acknowledge after any byte, then the slave transmitter must release the SDA line to let the master generate the Stop condition. 2.1.5 Data After the first byte containing the address, all bytes that follow are data bytes. Each byte must be followed by an acknowledge bit. Data is transferred MSB-first. 14 Data Sheet 2.1.6 Stop Condition MVTX2801 Generated by the master. The bus is considered to be free after the Stop condition is generated. The Stop condition occurs if while the SCL line is High, there is a Low-to-High transition of the SDA line. The I2C interface serves the function of configuring the MVTX2801 at boot time. The master is the MVTX2801, and the slave is the EEPROM memory. 2.2 Synchronous Serial Interface The synchronous serial interface serves the function of configuring the MVTX2801 not at boot time but via a PC. The PC serves as master and the MVTX2801 serves as slave. The protocol for the synchronous serial interface is nearly identical to the I2C protocol. The main difference is that there is no acknowledgment bit after each byte of data transferred. The unmanaged MVTX2801 uses a synchronous serial interface to program the internal registers. To reduce the number of signals required, the register address, command and data are shifted in serially through the PS_DO pin. PS_STROBE- pin is used as the shift clock. PS_DI- pin is used as data return path. Each command consists of four parts. * START pulse * Register Address * Read or Write command * Data to be written or read back Any command can be aborted in the middle by sending an ABORT pulse to the MVTX2801. A START command is detected when PS_DO is sampled high at PS_STROBE - leading edge, and PS_DO is sampled low when STROBE- falls. An ABORT command is detected when PS_DO is sampled low at PS_STROBE - leading edge, and PS_DO is sampled high when PS_STROBE - falls. 2.2.1 Write Command PS-STROBE2 Extra clocks after last transfer PS_DO A0 START A1 A2 ... A9 A10 A11 W D0 D1 D2 D3 D4 D5 D6 D7 DATA ADDRESS COMMAND Figure 3 - Write Command 15 MVTX2801 2.2.2 Read Command Data Sheet PS_STROBE- PS_DO A0 A1 A2 ... A0 A1 A2 ... A10 A11 A9 A10 A11 A9 R DATA START PS_DI ADDRESS COMMAND D0 D1 D2 D3 D4 D5 D6 D7 Figure 4 - Read Command All registers in the MVTX2801 can be modified through this synchronous serial interface. 3.0 3.1 Data Forwarding Protocol Unicast Data Frame Forwarding When a frame arrives, it is assigned a handle in memory by the Frame Control Buffer Manager (FCB Manager). An FCB handle will always be available, because of advance buffer reservations. The memory (ZBT-SRAM) interface is a 64-bit bus, connected to a ZBT-SRAM domain. The Receive DMA (RxDMA) is responsible for multiplexing the data and the address. On a port's "turn," the RxDMA will move 8 bytes (or up to the end-of-frame) from the port's associated RxFIFO into memory (Frame Data Buffer, or FDB). Once an entire frame has been moved to the FDB, and a good end-of-frame (EOF) has been received, the Rx interface makes a switch request. The RxDMA arbitrates among multiple switch requests. The switch request consists of the first 64 bytes of a frame, containing among other things, the source and destination MAC addresses of the frame. The search engine places a switch response in the switch response queue of the frame engine when done. Among other information, the search engine will have resolved the destination port of the frame and will have determined that the frame is unicast. After processing the switch response, the Transmission Queue Manager (TxQ manager) of the frame engine is responsible for notifying the destination port that it has a frame to forward to it. But first, the TxQ manager has to decide whether or not to drop the frame, based on global FDB reservations and usage, as well as TxQ occupancy at the destination. If the frame is not dropped, then the TxQ manager links the frame's FCB to the correct per-port-per-class TxQ. Unicast TxQ's are linked lists of transmission jobs, represented by their associated frames' FCB's. There is one linked list for each transmission class for each port. There are 8 classes for each of the 4 Gigabit ports - a total of 32 unicast queues. The TxQ manager is responsible for scheduling transmission among the queues representing different classes for a port. When the port control module determines that there is room in the MAC Transmission FIFO (TxFIFO) for another frame, it requests the handle of a new frame from the TxQ manager. The TxQ manager chooses among the head-of-line (HOL) frames from the per-class queues for that port, using a Zarlink Semiconductor scheduling algorithm. 16 Data Sheet MVTX2801 As at the transmit end, each of the 4 ports has time slots devoted solely to reading data from memory at the address calculated by port control. The Transmission DMA (TxDMA) is responsible for multiplexing the data and the address. On a port's turn, the TxDMA will move 8 bytes (or up to the EOF) from memory into the port's associated TxFIFO. After reading the EOF, the port control requests a FCB release for that frame. The TxDMA arbitrates among multiple buffer release requests. The frame is transmitted from the TxFIFO to the line. 3.2 Multicast Data Frame Forwarding After receiving the switch response, the TxQ manager has to make the dropping decision. A global decision to drop can be made, based on global FDB utilization and reservations. If so, then the FCB is released and the frame is dropped. In addition, a selective decision to drop can be made, based on the TxQ occupancy at some subset of the multicast packet's destinations. If so, then the frame is dropped at some destinations but not others, and the FCB is not released. If the frame is not dropped at a particular destination port, then the TxQ manager formats an entry in the multicast queue for that port and class. Multicast queues are physical queues (unlike the linked lists for unicast frames). There are 4 multicast queues for each of the 4 Gigabit ports. During scheduling, the TxQ manager treats the unicast queue and the multicast queue of the same class as one logical queue. The port control requests a FCB release only after the EOF for the multicast frame has been read by all ports to which the frame is destined. 4.0 4.1 Memory Interface Overview The figure below illustrates the first part of the ZBT-SRAM interface for the MVTX2801. As shown, a 64 bit bus ZBT-SRAM bank A is used for Tx/RxDMA access. Because the clock frequency is 133 MHz, the total memory bandwidth is 64-bits x 133 MHz = 8.5 Gbps, for frame data buffer (FDB) access. ZBT-SRAM Bank A TX DMA 0-1 TX DMA 2-3 RX DMA 0-1 RX DMA 2-3 Figure 5 - SRAM Interface Block Diagram (DMAs for Gigabit Ports) 17 MVTX2801 4.2 Detailed Memory Information Data Sheet Because the memory bus is 64 bits wide, frames are broken into 8-byte granules, written to and read from each memory access. In the worst case, a 1-byte-long EOF granule gets written to memory Bank. This means that a 7-byte segment of memory bus is idle. The scenario results in a maximum 7 bytes of waste per frame, which is always acceptable because the interfame gap is 20 bytes. 5.0 5.1 Search Engine Search Engine Overview The MVTX2801 search engine is optimized for high throughput searching, with enhanced features to support: * * * Up to 64K MAC addresses 4 groups of port trunking Traffic classification into 8 transmission priorities, and 2 drop precedence levels 5.2 Basic Flow Shortly after a frame enters the MVTX2801 and is written to the Frame Data Buffer (FDB), the frame engine generates a Switch Request, which is sent to the search engine. The switch request consists of the first 64 bytes of the frame, which contain all the necessary information for the search engine to perform its task. When the search engine is done, it writes to the Switch Response Queue, and the frame engine uses the information provided in that queue for scheduling and forwarding. In performing its task, the search engine extracts and compresses the useful information from the 64-byte switch request. Among the information extracted are the source and destination MAC addresses, the transmission and discard priorities, whether the frame is unicast or multicast. Requests are sent to the external SRAM Switch Database to locate the associated entries in the external MCT table. When all the information has been collected from external SRAM, the search engine has to compare the MAC address on the current entry with the MAC address for which it is searching. If it is not a match, the process is repeated on the internal MCT Table. All MCT entries other than the first of each linked list are maintained internal to the chip. If the desired MAC address is still not found, then the result is either learning (source MAC address unknown) or flooding (destination MAC address unknown). If the destination MAC address belongs to a port trunk, then the trunk number is retrieved instead of the port number. But on which port of the trunk will the frame be transmitted? This is easily computed using a hash of the source and destination MAC addresses. When all the information is compiled, the switch response is generated, as stated earlier. 18 Data Sheet 5.3 5.3.1 Search, Learning, and Aging MAC Search MVTX2801 The search block performs source MAC address and destination MAC address searching. As we indicated earlier, if a match is not found, then the next entry in the linked list must be examined, and so on until a match is found or the end of the list is reached. In port based VLAN mode, a bitmap is used to determine whether the frame should be forwarded to the outgoing port. The bitmap is not dynamic. Ports cannot enter and exit groups dynamically. The MAC search block is also responsible for updating the source MAC address timestamp, used for aging. 5.3.2 Learning The learning module learns new MAC addresses and performs port change operations on the MCT database. The goal of learning is to update this database as the networking environment changes over time. Learning and port change will be performed based on memory slot availability only. 5.3.3 Aging Aging time is controlled by register 400h and 401h. The aging module scans and ages MCT entries based on a programmable "age out" time interval. As we indicated earlier, the search module updates the source MAC address and VLAN port association timestamps for each frame it processes. When an entry is ready to be aged, the entry is removed from the table. 5.3.4 Data Structure The MCT data structure is used for searching for MAC addresses. The structure is maintained by hardware in the search engine. The database is essentially a hash table, with collisions resolved by chaining. The database is partially external, and partially internal, as described earlier: the first MCT entry of each linked list is always located in the external SRAM, and the subsequent MCTs are located internally. 19 MVTX2801 6.0 6.1 * * * * Data Sheet Frame Engine Data Forwarding Summary * * Enters the device at the RxMAC, the RxDMA will move the data from the MAC RxFIFO to the FDB. Data is moved in 8-byte granules in conjunction with the scheme for the SRAM interface. A switch request is sent to the Search Engine. The Search Engine processes the switch request. A switch response is sent back to the Frame Engine and indicates whether the frame is unicast or multicast, and its destination port or ports. A Transmission Scheduling Request is sent in the form of a signal notifying the TxQ manager. Upon receiving a Transmission Scheduling Request, the device will format an entry in the appropriate Transmission Scheduling Queue (TxSch Q) or Queues. There are 8 TxSch Queues for each Gigabit port, one for each priority. Creation of a queue entry either involves linking a new job to the appropriate linked list if unicast, or adding an entry to a physical queue if multicast. When the port is ready to accept the next frame, the TxQ manager will get the head-of-line (HOL) entry of one of the TxSch Qs, according to the transmission scheduling algorithm (so as to ensure per-class quality of service). The unicast linked list and the multicast queue for the same port-class pair are treated as one logical queue. The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of the destination port. 6.2 Frame Engine Details This section briefly describes the functions of each of the modules of the MVTX2801 frame engine. 6.2.1 FCB Manager The FCB manager allocates FCB handles to incoming frames, and releases FCB handles upon frame departure. The FCB manager is also responsible for enforcing buffer reservations and limits. The default values can be determined by referring to Chapter 8. In addition, the FCB manager is responsible for buffer aging, and for linking unicast forwarding jobs to their correct TxSch Q. The buffer aging can be enabled or disabled by the bootstrap pin and the aging time is defined in register FCBAT. 6.2.2 Rx Interface The Rx interface is mainly responsible for communicating with the RxMAC. It keeps track of the start and end of frame and frame status (good or bad). Upon receiving an end of frame that is good, the Rx interface makes a switch request. 6.2.3 RxDMA The RxDMA arbitrates among switch requests from each Rx interface. It also buffers the first 64 bytes of each frame for use by the search engine when the switch request has been made. 6.2.4 TxQ Manager First, the TxQ manager checks the per-class queue status and global Reserved resource situation, and using this information, makes the frame dropping decision after receiving a switch response. If the decision is not to drop, the TxQ manager requests that the FCB manager link the unicast frame's FCB to the correct per-port-per-class TxQ. If multicast, the TxQ manager writes to the multicast queue for that port and class. The TxQ manager can also trigger source port flow control for the incoming frame's source if that port is flow control enabled. Second, the TxQ manager handles transmission scheduling; it schedules transmission among the queues representing different classes for a port. Once a frame has been scheduled, the TxQ manager reads the FCB information and writes to the correct port control module. 20 Data Sheet 6.3 Port Control MVTX2801 The port control module calculates the SRAM read address for the frame currently being transmitted. It also writes start of frame information and an end of frame flag to the MAC TxFIFO. When transmission is done, the port control module requests that the buffer be released. 6.4 TxDMA The TxDMA multiplexes data and address from port control, and arbitrates among buffer release requests from the port control modules. 7.0 7.1 Quality of Service and Flow Control Model Quality of service (QoS) is an all-encompassing term for which different people have different interpretations. In this chapter, by quality of service assurances, we mean the allocation of chip resources so as to meet the latency and bandwidth requirements associated with each traffic class. We do not presuppose anything about the offered traffic pattern. If the traffic load is light, then ensuring quality of service is straightforward. But if the traffic load is heavy, the MVTX2801 must intelligently allocate resources so as to assure quality of service for high priority data. We assume that the network manager knows his applications, such as voice, file transfer, or web browsing, and their relative importance. The manager can then subdivide the applications into classes and set up a service contract with each. The contract may consist of bandwidth or latency assurances per class. Sometimes it may even reflect an estimate of the traffic mix offered to the switch, though this is not required. The table below shows examples of QoS applications with eight transmission priorities, including best effort traffic for which we provide no bandwidth or latency assurances. Class Example Assured Bandwidth (user defined) Low Drop Subclass (If class is oversubscribed, these packets are the last to be dropped.) High Drop Subclass (If class is oversubscribed, these packets are the first to be dropped.) Highest transmission priorities, P7 Latency < 200 s Highest transmission priorities, P6 Latency < 200 s Middle transmission priorities, P5 Latency < 400 s Middle transmission priorities, P4 Latency < 800 s Low transmission priorities, P3 Latency < 1600 s 300 Mbps Sample application: control information Sample applications: phone calls; circuit emulation Sample application: interactive activities Sample application: web business Sample application: file backups Sample application: training video; other multimedia Sample application: non-critical interactive activities 200 Mbps 125 Mbps 250 Mbps 80 Mbps Table 1 - Two-dimensional World Traffic 21 MVTX2801 Class Example Assured Bandwidth (user defined) Low Drop Subclass (If class is oversubscribed, these packets are the last to be dropped.) Data Sheet High Drop Subclass (If class is oversubscribed, these packets are the first to be dropped.) Low transmission priorities, P2 Latency < 3200 s Best effort, P1-P0 TOTAL 45 Mbps Sample application: email Sample application: web research 1 Gbps Sample application: casual web browsing Table 1 - Two-dimensional World Traffic (continued) It is possible that a class of traffic may attempt to monopolize system resources by sending data at a rate in excess of the contractually assured bandwidth for that class. A well-behaved class offers traffic at a rate no greater than the agreed-upon rate. By contrast, a misbehaving class offers traffic that exceeds the agreed-upon rate. A misbehaving class is formed from an aggregation of misbehaving microflows. To achieve high link utilization, a misbehaving class is allowed to use any idle bandwidth. However, the quality of service (QoS) received by well-behaved classes must never suffer. As Table 1 illustrates, each traffic class may have its own distinct properties and applications. As shown, classes may receive bandwidth assurances or latency bounds. In the example, P7, the highest transmission class, requires that all frames be transmitted within 0.2 ms, and receives 30% of the 1 Gbps of bandwidth at that port. Best-effort (P1-P0) traffic forms a lower tier of service that only receives bandwidth when none of the other classes have any traffic to offer. In addition, each transmission class has two subclasses, high-drop and low-drop. Well-behaved users should not lose packets. But poorly behaved users, users who send data at too high a rate, will encounter frame loss, and the first to be discarded will be high-drop. Of course, if this is insufficient to resolve the congestion, eventually some low-drop frames are dropped as well. Table 1 shows that different types of applications may be placed in different boxes in the traffic table. For example, web search may fit into the category of high-loss, high-latency-tolerant traffic, whereas VoIP fits into the category of low-loss, low-latency traffic. 7.2 Four QoS Configurations There are four basic pieces to QoS scheduling in the MVTX2801: strict priority (SP), delay bound, weighted fair queuing (WFQ), and best effort (BE). Using these four pieces, there are four different modes of operation, as shown in Table 2. P7 Op1 (default) Op2 Op3 Op4 P6 P5 P4 P3 P2 P1 BE Delay Bound WFQ BE P0 Delay Bound SP SP WFQ Table 2 - Four QoS configurations per port The default configuration is six delay-bounded queues and two best-effort queues. The delay bounds per class are 0.16 ms for P7 and P6, 0.32 ms for P5, 0.64 ms for P4, 1.28 ms for P3, and 2.56 ms for P2. Best effort traffic is only served when there is no delay-bounded traffic to be served. P1 has strict priority over P0. 22 Data Sheet MVTX2801 We have a second configuration in which there are two strict priority queues, four delay bounded queues, and two best effort queues. The delay bounds per class are 0.32 ms for P5, 0.64 ms for P4, 1.28 ms for P3, and 2.56 ms for P2. If the user is to choose this configuration, it is important that P7-P6 (SP) traffic be either policed or implicitly bounded (e.g. if the incoming SP traffic is very light and predictably patterned). Strict priority traffic, if not admission-controlled at a prior stage to the MVTX2801, can have an adverse effect on all other classes' performance. P7 and P6 are both SP classes, and P7 has strict priority over P6. The third configuration contains two strict priority queues and six queues receiving a bandwidth partition via WFQ. As in the second configuration, strict priority traffic needs to be carefully controlled. In the fourth configuration, all queues are served using a WFQ service discipline 7.3 Delay Bound In the absence of a sophisticated QoS server and signaling protocol, the MVTX2801 may not be assured of the mix of incoming traffic ahead of time. To cope with this uncertainty, our delay assurance algorithm dynamically adjusts its scheduling and dropping criteria, guided by the queue occupancies and the due dates of their head-of-line (HOL) frames. As a result, we assure latency bounds for all admitted frames with high confidence, even in the presence of system-wide congestion. Our algorithm identifies misbehaving classes and intelligently discards frames at no detriment to well-behaved classes. Our algorithm also differentiates between high-drop and low-drop traffic with a weighted random early drop (WRED) approach. Random early dropping prevents congestion by randomly dropping a percentage of high-drop frames even before the chip's buffers are completely full, while still largely sparing low-drop frames. This allows high-drop frames to be discarded early, as a sacrifice for future low-drop frames. Finally, the delay bound algorithm also achieves bandwidth partitioning among classes. 7.4 Strict Priority and Best Effort When strict priority is part of the scheduling algorithm, if a queue has even one frame to transmit, it goes first. Two of our four QoS configurations include strict priority queues. The goal is for strict priority classes to be used for IETF expedited forwarding (EF), where performance guarantees are required. As we have indicated, it is important that strict priority traffic be either policed or implicitly bounded, so as to keep from harming other traffic classes. When best effort is part of the scheduling algorithm, a queue only receives bandwidth when none of the other classes have any traffic to offer. Two of our four QoS configurations include best effort queues. The goal is for best effort classes to be used for non-essential traffic, because we provide no assurances about best effort performance. However, in a typical network setting, much best effort traffic will indeed be transmitted, and with an adequate degree of expediency. Because we do not provide any delay assurances for best effort traffic, we do not enforce latency by dropping best effort traffic. Furthermore, because we assume that strict priority traffic is carefully controlled before entering the MVTX2801, we do not enforce a fair bandwidth partition by dropping strict priority traffic. To summarize, dropping to enforce quality of service (i.e. bandwidth or delay) does not apply to strict priority or best effort queues. We only drop frames from best effort and strict priority queues when global buffer resources become scarce. 7.5 Weighted Fair Queuing In some environments - for example, in an environment in which delay assurances are not required, but precise bandwidth partitioning on small time scales is essential (WFQ may be preferable to a delay-bounded scheduling discipline). The MVTX2801 provides the user with a WFQ option with the understanding that delay assurances cannot be provided if the incoming traffic pattern is uncontrolled. The user sets eight WFQ "weights" such that all weights are whole numbers and sum to 64. This provides per-class bandwidth partitioning with error within 2%. In WFQ mode, though we do not assure frame latency, the MVTX2801 still retains a set of dropping rules that helps to prevent congestion and trigger higher level protocol end-to-end flow control. As before, when strict priority is combined with WFQ, we do not have special dropping rules for the strict priority 23 MVTX2801 Data Sheet queues, because the input traffic pattern is assumed to be carefully controlled at a prior stage. However, we do indeed drop frames from SP queues for global buffer management purposes. In addition, queues P1 and P0 are treated as best effort from a dropping perspective, though they still are assured a percentage of bandwidth from a WFQ scheduling perspective. What this means is that these particular queues are only affected by dropping when the global buffer count becomes low. 7.6 Shaper Although traffic shaping is not a primary function of the MVTX2801, the chip does implement a shaper for expedited forwarding (EF). Our goal in shaping is to control the peak and average rate of traffic exiting the MVTX2801. Shaping is limited to class P6 (the second highest priority). This means that class P6 will be the class used for EF traffic. (By contrast, we assume class P7 will be used for control packets only.) If shaping is enabled for P6, then P6 traffic must be scheduled using strict priority. With reference to Table 2, only the middle two QoS configurations may be used. Peak rate is set using a programmable whole number, no greater than 64 (register QOS-CREDIT_C6_Gn). For example, if the setting is 32, then the peak rate for shaped traffic is 32/64 x 1000 Mbps = 500 Mbps. Average rate is also a programmable whole number, no greater than 64, and no greater than the peak rate. For example, if the setting is 16, then the average rate for shaped traffic is (16/64) x 1000 Mbps = 250 Mbps. As a consequence of the above settings in our example, shaped traffic will exit the MVTX2801 at a rate always less than 500 Mbps, and averaging no greater than 250 Mbps. Also, when shaping is enabled, it is possible for a P6 queue to explode in length if fed by a greedy source. The reason is that a shaper is by definition not work-conserving; that is, it may hold back from sending a packet even if the line is idle. Though we do have global resource management, we do nothing to prevent this situation locally. We assume SP traffic is policed at a prior stage to the MVTX2801. 7.7 WRED Drop Threshold Management Support To avoid congestion, the Weighted Random Early Detection (WRED) logic drops packets according to specified parameters. The following table summarizes the behavior of the WRED logic. P7 Level 1 N > 240 Level 2 N > 280 Level 3 N > 320 |P7| > A KB P6 P5 P4 P3 P2 High Drop X% Low Drop 0% Z% 100% |P6| > B KB |P5| > C KB |P4| > D KB |P3| > E KB |P2| > F KB Y% 100% Table 3 - WRED Dropping Scheme In the table, |Px| is the byte count in queue Px. The WRED logic has three drop levels, depending on the value of N, which is based on the number of bytes in the priority queues. If delay bound scheduling is used, N equals 16|P7| + 16|P6| + 8|P5| + 4|P4| + 2|P3| + |P2|. If WFQ scheduling is used, N equals |P7| + |P6| + |P5| + |P4| + |P3| + |P2|. Each drop level has defined high-drop and low-drop percentages, which indicate the percentage of high-drop and low-drop packets that will be dropped at that level. The X, Y, and Z percent parameters can be programmed using the registers RDRC0 and RDRC1. Parameters A-F are the byte count thresholds for each priority queue, and are also programmable. When using delay bound scheduling, the values selected for A-F also control the approximate bandwidth partition among the traffic classes; see application note. 24 Data Sheet 7.8 Buffer Management MVTX2801 Because the number of frame data buffer (FDB) slots is a scarce resource, and because we want to ensure that one misbehaving source port or class cannot harm the performance of a well-behaved source port or class, we introduce the concept of buffer management into the MVTX2801. Our buffer management scheme is designed to divide the total buffer space into numerous reserved regions and one shared pool (see Figure 6). As shown in the figure, the FDB pool is divided into several parts. A reserved region for temporary frames stores frames prior to receiving a switch response. Such a temporary region is necessary, because when the frame first enters the MVTX2801, its destination port and class are as yet unknown, and so the decision to drop or not needs to be temporarily postponed. This ensures that every frame can be received first before subjecting it to the frame drop discipline after classifying. Six reserved sections, one for each of the highest six priority classes, ensure a programmable number of FDB slots per class. The lowest two classes do not receive any buffer reservation. Another segment of the FDB reserves space for each of the 4 ports. These source port buffer reservations are programmable. These 8 reserved regions make sure that no well-behaved source port can be blocked by another misbehaving source port. In addition, there is a shared pool, which can store any type of frame. The registers related to the Buffer Management logic are: * * * * * * * * PRG- Port Reservation for Gigabit Ports SFCB- Share FCB Size C2RS- Class 2 Reserved Size C3RS- Class 3 Reserved Size C4RS- Class 4 Reserved Size C5RS- Class 5 Reserved Size C6RS- Class 6 Reserved Size C7RS- Class 7 Reserved Size Temporary Reservation RTMP Per-Class Reservations Rp7, Rp6 ... Rp2 Shared Pool S Per-Source Reservations 8 . R1G Figure 6 - Buffer Partition Scheme Used in the MVTX2801 25 MVTX2801 7.8.1 Dropping When Buffers Are Scarce Summarizing the two examples of local dropping discussed earlier in this chapter: Data Sheet If a queue is a delay-bounded queue, we have a multilevel WRED drop scheme, designed to control delay and partition bandwidth in case of congestion. * If a queue is a WFQ-scheduled queue, we have a multilevel WRED drop scheme, designed to prevent congestion. In addition to these reasons for dropping, the MVTX2801 also drops frames when global buffer space becomes scarce. The function of buffer management is to ensure that such droppings cause as little blocking as possible. * 7.9 Flow Control Basics Because frame loss is unacceptable for some applications, the MVTX2801 provides a flow control option. When flow control is enabled, scarcity of buffer space in the switch may trigger a flow control signal; this signal tells a source port, sending a packet to this switch, to temporarily hold off. While flow control offers the clear benefit of no packet loss, it also introduces a problem for quality of service. When a source port receives an Ethernet flow control signal, all microflows originating at that port, well-behaved or not, are halted. A single packet destined for a congested output can block other packets destined for uncongested outputs. The resulting head-of-line blocking phenomenon means that quality of service cannot be assured with high confidence when flow control is enabled. In the MVTX2801, each source port can independently have flow control enabled or disabled. For flow control enabled ports, by default all frames are treated as lowest priority during transmission scheduling. This is done so that those frames are not exposed to the WRED Dropping scheme. Frames from flow control enabled ports feed to only one queue at the destination, the queue of lowest priority. What this means is that if flow control is enabled for a given source port, then we can guarantee that no packets originating from that port will be lost, but at the possible expense of minimum bandwidth or maximum delay assurances. In addition, these "downgraded" frames may only use the shared pool or the per-source reserved pool in the FDB; frames from flow control enabled sources may not use reserved FDB slots for the highest six classes (P2-P7). The MVTX2801 does provide a system-wide option of permitting normal QoS scheduling (and buffer use) for frames originating from flow control enabled ports. When this programmable option is active, it is possible that some packets may be dropped, even though flow control is on. The reason is that intelligent packet dropping is a major component of the MVTX2801's approach to ensuring bounded delay and minimum bandwidth for high priority flows. 7.9.1 Unicast Flow Control For unicast frames, flow control is triggered by source port resource availability. Recall that the MVTX2801's buffer management scheme allocates a reserved number of FDB slots for each source port. If a programmed number of a source port's reserved FDB slots have been used, then flow control Xoff is triggered. Xon is triggered when a port is currently being flow controlled, and all of that port's reserved FDB slots have been released. Note that the MVTX2801's per-source-port FDB reservations assure that a source port that sends a single frame to a congested destination will not be flow controlled. 7.9.2 Multicast Flow Control When port based Vlan is not used, a global buffer counter (64 packets) triggers flow control for multicast frames. When the system exceeds a programmable threshold of multicast packets, Xoff is triggered. Xon is triggered when the system returns below this threshold. MCC register programs the threshold. When port based Vlan is used, each Vlan has a global buffer counter. In addition, each source port has an 8-bit port map recording which port or ports of the multicast frame's fanout were congested at the time Xoff was triggered. All ports are continuously monitored for congestion, and a port is identified as uncongested when its queue occupancy falls below a fixed threshold. When all those ports that were originally 26 Data Sheet MVTX2801 marked as congested in the port map have become uncongested, then Xon is triggered, and the 8-bit vector is reset to zero. The MVTX2801 also provides the option of disabling VLAN multicast flow control. Note: If port flow control is on, QoS performance will be affected. To determine the most efficient way to program, please refer to the QoS Application Note. 7.10 Mapping to IETF Diffserv Classes The mapping between priority classes discussed in this chapter and elsewhere is shown below. MVTX2801 IETF P7 NM P6 EF P5 AF0 P4 AF1 P3 AF2 P2 AF3 P1 BE0 P0 BE1 Table 4 - Mapping between MVTX2801 and IETF Diffserv Classes for Gigabit Ports As the table illustrates, P7 is used solely for network management (NM) frames. P6 is used for expedited forwarding service (EF). Classes P2 through P5 correspond to an assured forwarding (AF) group of size 4. Finally, P0 and P1 are two best effort (BE) classes. Features of the MVTX2801 that correspond to the requirements of their associated IETF classes are summarized in the table below. Network management (NM) and Expedited forwarding (EF) * * * * * * * Global buffer reservation for NM and EF Shaper for EF traffic Option of strict priority scheduling No dropping if admission controlled Four AF classes Programmable bandwidth partition, with option of WFQ service Option of delay-bounded service keeps delay under fixed levels even if not admission-controlled Random early discard, with programmable levels Global buffer reservation for each AF class Two BE classes Service only when other queues are idle means that QoS not adversely affected Random early discard, with programmable levels Traffic from flow control enabled ports automatically classified as BE Assured forwarding (AF) * * Best effort (BE) * * * * Table 5 - MVTX2801 Features Enabling IETF Diffserv Standards 27 MVTX2801 8.0 8.1 Data Sheet Port Trunking Features and Restrictions A port group (i.e. trunk) can include up to 4 physical ports, but all of the ports in a group must be in the same MVTX2801. The MVTX2801 provides several pre-assigned trunk group options, containing as many as 4 ports per group, or alternatively, as many as 4 total groups. Load distribution among the ports in a trunk for unicast is performed using hashing based on source MAC address and destination MAC address. The other options include source MAC address only, destination MAC address only. Load distribution for multicast is performed similarly. If a VLAN includes any of the ports in a trunk group, all the ports in that trunk group should be in the same VLAN member map. The MVTX2801 also provides a safe fail-over mode for port trunking automatically. If one of the ports in the trunking group goes down, the MVTX2801 will automatically redistribute the traffic over to the remaining ports in the trunk in unmanaged mode. In managed mode, the software can perform similar tasks. 8.2 Unicast Packet Forwarding The search engine finds the destination MCT entry, and if the status field says that the destination address found belongs to a trunk, then the group number is retrieved instead of the port number. In addition, if the source address belongs to a trunk, then the source port's trunk membership register is checked to determine if the address has moved. A hash key is used to determine the appropriate forwarding port, based on some combination of the source and destination MAC addresses for the current packet. The search engine retrieves the VLAN member ports from the VLAN index table, which consists of 4K entries. The search engine retrieves the VLAN member ports from the ingress port's VLAN map. Based on the destination MAC address, the search engine determines the egress port from the MCT database. If the egress port is a member of a trunk group, the packet can be distributed to the other members of that trunk group. The VLAN map is used to check whether the egress port is a member of the VLAN, based on the ingress port. If it is a member, the packet is forwarded otherwise it is discarded. 8.3 Multicast Packet Forwarding For multicast packet forwarding, the device must determine the proper set of ports from which to transmit the packet based on the VLAN index and hash key. Two functions are required in order to distribute multicast packets to the appropriate destination ports in a port trunking environment. * * Determining one forwarding port per group. For multicast packets, all but one port per group, the forwarding port, must be excluded. 28 Data Sheet 8.4 MVTX2801 Preventing Multicast Packets from Looping Back to the Source Trunk The search engine needs to prevent a multicast packet from sending to a port that is in the same trunk group with the source port. This is because, when we select the primary forwarding port for each group, we do not take the source port into account. To prevent this, we simply apply one additional filter, so as to block that forwarding port for this multicast packet. 9.0 9.1 LED Interface Introduction The MVTX2801 LED block provides two interfaces: a serial output channel, and a parallel time-division interface. The serial output channel provides port status information from the MVTX2801 chip in a continuous serial stream. This means that a low cost external device must be used to decode the serial data and to drive an LED array for display. By contrast, the parallel time-division interface supports a glueless LED module. Indeed, the parallel interface can directly drive low-current LEDs without any extra logic. The pin LED_PM is used to select serial or parallel mode. For some LED signals, the interface also provides a blinking option. Blinking may be enabled for LED signals TxD, RxD, COL, and FC (to be described later). The pin LED_BLINK is used to enable blinking, and the blinking frequency is around 160 ms. 9.2 Serial Mode In serial mode, the following pins are utilized: * LED_SYNCO - a sync pulse that defines the boundary between status frames * LED_CLKO - the clock signal * LED_DO - a continuous serial stream of data for all status LEDs that repeats once every frame time In each cycle (one frame of status information, or one sync pulse), 16x8 bits of data are transmitted on the LED_DO signal. The sequence of transmission of data bits is as shown in the figure below: LE_SYNCO LE_DO P0 info P1 info P2 info P3 info P4 info P5 info P6 info P7 info U0 U1 U2 U3 U4 U5 U6 U7 LE_CLKO 0 FC 1 TxD 2 RxD 3 LNK 4 SP0 5 SP1 6 FDX 7 COL Figure 7 - Timing diagram for serial mode in LED interface. The status bits shown in here are flow control (FC), transmitting data (TxD), receiving data (RxD), link up (LNK), speed (SP0 and SP1), full duplex (FDX), and collision (COL). Note that SP[1:0] is defined as 10 for 1 Gbps, 01 for 100 Mbps, and 00 for 10 Mbps. 29 MVTX2801 Data Sheet Also note that U0-U7 represent user-defined sub-frames in which additional status information may be embedded. We will see later that the MVTX2801 provides registers that can be written by the CPU to indicate this additional status information as it becomes available. 9.3 Parallel Mode In parallel mode, the following pins are utilized: LED_PORT_SEL[3:0] - indicates which of the 4 Gigabit port status bytes is being read out LED_PORT_SEL[7:4] - No use. LED_PORT_SEL[9:8] - indicates which of the 2 user-defined status bytes is being read out LED_BYTEOUT_[7:0] - provides 8 bits for 4 different port status indicators. Note that these bits are active low. By default, the system is in parallel mode. In parallel mode, the 10 status bytes are scanned in a continuous loop, with one byte read out per clock cycle, and the appropriate port select bit asserted. * * * * 9.4 LED Control Registers An LED Control Register can be used for programming the LED clock rate, sample hold time, and pattern in parallel mode. In addition, the MVTX2801 provides 8 registers called LEDUSER[7:0] for user-defined status bytes. During operation, the CPU can write values to these registers, which will be read out to the LED interface output (serial or parallel). Only LEDUSER[1:0] are used in parallel mode. The content of the LEDUSER registers will be sent out by the LED serial shift logic, or in parallel mode, a byte at a time. Because in parallel mode there are only two user-defined registers, LEDUSER[7:2] is shared with LEDSIG[7:2]. For LEDSIG[j], where j = 2, 3, ..., 6, the corresponding register is used for programming the LED pin LED_BYTEOUT_[j]. The format is as follows: 7 COL FDX SP1 4 SP0 3 COL FDX SP1 0 SP0 Bits [3:0] Signal polarity: 0: do not invert polarity (high true) 1: invert polarity Signal select: 0: do not select 1: select the corresponding bit Bits [7:4] For j = 2, 3, ..., 5, the value of LED_BYTEOUT_[j] equals the logical AND of all selected bits. For j = 6, the value is equal to the logical OR. Therefore, the programmable LEDSIG[5:2] registers allow any conjunctive formula including any of the 4 status bits (COL, FDX, SP1, SP0) or their negations to be sent to the LED_BYTEOUT_[5:2] pins. Similarly, the programmable LEDSIG[6] register allows any disjunctive formula including any of the 4 status bits or their negations to be sent to pin LED_BYTEOUT_[6]. LEDSIG[7] is used for programming both LED_BYTEOUT_[1] and LED_BYTEOUT_[0]. As we will see, it has other functions as well. The format is as follows: 30 Data Sheet 7 GP Bits [7] * RxD TxD 4 FC 3 P6 RxD TxD 0 FC MVTX2801 Global output polarity: this bit controls the output polarity of all LED_BYTEOUT_ and LED_PORT_SEL pins. (Default 0) - 0: do not invert polarity (LED_BYTEOUT_[7:0] are high activated; LED_PORT_SEL[9:0] are low activated) - 1: invert polarity (LED_BYTEOUT_[7:0] are low activated; LED_PORT_SEL[9:0] are high activated) Bits [6:4] * Signal select: - 0: do not select - 1: select the corresponding bit * Bit [3] * The value of LED_BYTEOUT_[1] equals the logical OR of all selected bits. (Default 110) Polarity control of LED_BYTEOUT_[6] (Default 0) - 0: do not invert - 1: invert Bits [2:0] * Signal select: - 0: do not select - 1: select the corresponding bit * The value of LED_BYTEOUT_[0] equals the logical OR of all selected bits. (Default 001) 31 MVTX2801 10.0 10.1 Data Sheet Register Definition Register Description Register Description CPU Addr (Hex) I2C R/W Addr (Hex) Default Notes 0. ETHERNET Port Control Registers - Substitute [N] with Port number (0..3) ECR1P"N" ECR2P"N" GGCONTROL0 GGCONTROL1 ACTIVELINK Port Control Register 1 for Port N Port Control Register 2 for Port N Extra Gigabit Port Control -port 0,1 Extra Gigabit Port Control -port 2,3 Active Link status port 3:0 000 + 2N 001 + 2N 012 013 016 R/W R/W R/W R/W R/W 000+2N 001+2N N/A N/A N/A c0 00 00 00 00 1. VLAN Control Registers - Substitute [N] with Port number (0..3) AVTCL AVTCH PVMAP"N"_0 PVMAP"N"_3 PVMODE 2. TRUNK Control Registers TRUNK0_MODE TRUNK1_MODE 3. CPU Port Configuration TX_AGE 4. Search Engine Configurations AGETIME_LOW AGETIME_HIGH SE_OPMODE MAC Address Aging Time Low MAC Address Aging Time High Search Engine operation mode 400 401 403 R/W R/W R/W 03C 03D NA 2c 00 00 Transmission Queue Aging Time 312 R/W 03B 08 Trunk Group 0 Mode Trunk Group 1 Mode 207 20E R/W R/W 039 03A 00 00 VLAN Type Code Register Low VLAN Type Code Register High Port "N" Configuration Register 0 Port "N" Configuration Register 3 VLAN Operating Mode 100 101 102 + 4N 105 + 4N 126 R/W R/W R/W R/W R/W 012 013 014+4N 017+4N 038 00 81 ff 00 00 5. Buffer Control and QOS Control FCBAT QOSC FCR AVPML AVPMM AVPMH TOSPML TOSPMM TOSPMH AVDM FCB Aging Timer QOS Control Flooding Control Register VLAN Priority Map Low VLAN Priority Map Middle VLAN Priority Map High TOS Priority Map Low TOS Priority Map Middle TOS Priority Map High VLAN Discard Map 500 501 502 503 504 505 506 507 508 509 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 03E 03F 040 041 042 043 044 045 046 047 ff 00 08 88 c6 fa 88 c6 fa 00 Table 6 - MVTX2801 Register Description 32 Data Sheet Register TOSDML BMRC UCC MCC PR100 PRG SFCB C2RS C3RS C4RS C5RS C6RS C7RS QOSC"N" QOSC"N" RDRC0 RDRC1 6. MISC Configuration Register MII_OP0 MII_OP1 FEN MIIC0 MIIC1 MIIC2 MIIC3 MIID0 MIID1 LED CHECKSUM LEDUSER0 LEDUSER1 LEDUSER2 LEDUSER3 LEDUSER4 MII Register Option 0 MII Register Option 1 Feature Registers MII Command Register 0 MII Command Register 1 MII Command Register 2 MII Command Register 3 MII Data Register 0 MII Data Register 1 LED Control Register EEPROM Checksum Register LED User Define Register 0 LED User Define Register 1 LED User Define Reg. 2/LED_byte pin 2 LED User Define Reg. 3/LED_byte pin 3 LED User Define Reg. 4/LED_byte pin 4 600 601 602 603 604 605 606 607 608 609 60B 60C 60D 60E 60F 610 R/W R/W R/W R/W R/W R/W R/W RO RO R/W R/W R/W R/W R/W R/W R/W 0B1 0B2 0B3 N/A N/A N/A N/A N/A N/A 0B4 0C5 0BB 0BC 0BD 0BE 0BF MVTX2801 Description TOS Discard Map Broadcast/Multicast Rate Control Unicast Congestion Control Multicast Congestion Control Port Reservation for 10/100 Ports Port Reservation for Giga Ports Share FCB Size Class 2 Reserved Size Class 3 Reserved Size Class 4 Reserved Size Class 5 Reserved Size Class 6 Reserved Size Class 7 Reserved Size QOS Control (N=0 - 2F) QOS Control (N=30 - 82) WRED Rate Control 0 WRED Rate Control 1 CPU Addr (Hex) 50A 50B 50C 50D 50E 50F 510 511 512 513 514 515 516 517-546 547-599 59A 59B I2C R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Addr (Hex) 048 049 04A 04B 04C 04D 04E 04F 050 051 052 053 054 055-084 NA 085 086 Default 00 00 07 48 00 26 37 00 00 00 00 00 00 Notes 8e 68 00 00 10 00 00 00 00 00 00 38 00 00 00 80 33 32 Table 6 - MVTX2801 Register Description (continued) 33 MVTX2801 Register LEDUSER5 LEDUSER6 LEDUSER7 MIINP0 MIINP1 E. Test Group Control DTSRL DTSRM DTSRH TDRB0 TDRB1 DTCR MASK0 MASK1 MASK2 MASK3 MASK4 F. Device Configuration Register GCR DCR DCR01 DCR23 DCR45 DCR67 DPST DTST PLLCR LCLKCR BCLKCR BSTRRB0 BSTRRB1 BSTRRB2 BSTRRB3 Global Control Register Device Status and Signature Register Gigabit Port0 Port1 Status Register Gigabit Port2 Port3 Status Register Gigabit Port4 Port5 Status Register Gigabit Port6 Port7 Status Register Device Port Status Register Data read back register PLL Control Register LCLK Control Register BCLK Control Register BOOT STRAP read back register 0 BOOT STRAP read back register 1 BOOT STRAP read back register 2 BOOT STRAP read back register 3 F00 F01 F02 F03 F04 F05 F06 F07 F08 F09 F0A F0B F0C F0D F0E R/W RO RO RO RO RO R/W RO R/W R/W R/W RO RO RO RO N/A N/A NA NA NA NA N/A N/A N/A N/A N/A N/A N/A N/A N/A 00 00 00 00 00 Test Register Low Test Register Medium Test Register High TEST MUX read back register [7:0] TEST MUX read back register [15:8] Test Counter Register MASK Timeout 0 MASK Timeout 1 MASK Timeout 2 MASK Timeout 3 MASK Timeout 4 E00 E01 E02 E03 E04 E05 E06 E07 E08 E09 E0A R/W R/W R/W RO RO R/W R/W R/W R/W R/W R/W N/A N/A N/A N/A N/A N/A 0B6 0B7 0B8 0B9 0BA 00 00 00 00 00 00 00 01 00 Data Sheet Description LED User Define Reg. 5/LED_byte pin 5 LED User Define Reg. 6/LED_byte pin 6 LED User Define Reg. 7/LED_byte pin 1 & 0 MII NEXT PAGE DATA REGISTER0 MII NEXT PAGE DATA REGISTER1 CPU Addr (Hex) 611 612 613 614 615 I2C R/W R/W R/W R/W R/W R/W Addr (Hex) 0C0 0C1 0C2 0C3 0C4 Default 20 40 61 00 00 Notes Table 6 - MVTX2801 Register Description (continued) 34 Data Sheet Register BSTRRB4 BSTRRB5 DA MVTX2801 Description BOOT STRAP read back register 4 BOOT STRAP read back register 5 DA Register CPU Addr (Hex) F0F F10 FFF I2C R/W RO RO RO Addr (Hex) N/A N/A N/A Default Notes da Table 6 - MVTX2801 Register Description (continued) Note: 1. se = Search Engine 2. fe = Frame Engine 3. pgs = Port Group01, 23, 45, and 67 4. mc = MAC Control 5. tm = timer 10.2 10.2.1 I2C Group 0 Address - MAC Ports Group ECR1Pn: Port N Control Register Address h00+2n; Serial Interface Address: h000+2n (n=0 to 3) (For the 2600 it is different) Accessed by serial interface and I2C (R/W) 7 Sp State Bit [4:0] Bit [4:3] * 6 5 A-FC 4 3 2 1 0 Port Mode Port Mode (Default 2'b00) - 00 - Automatic Enable Auto-Negotiation - This enables hardware state machine for auto-negotiation. - 01 - Limited Disable auto-Negotiation - This disables hardware for speed auto-negotiation. Hardware Polls MII for link status. - 10 - Link Down - Force link down (disable the port). Does not talk to PHY. - 11 - Link Up - Does not talk to PHY. User ERC1 [2:0] for config. - 1 - 10Mbps (Default 1'b0) - 0 - 100Mbps Bit [2] * Bit [1] Bit 2 is used only when the port is in MII (10/100) mode. - 1 - Half Duplex (Do not use) (Default 1'b0) - 0 - Full Duplex 35 MVTX2801 Bit [0] * * - 1 - Flow Control Off (Default 1'b0) - 0 - Flow Control On Data Sheet * * When flow control is on: In full duplex mode, the MAC transmitter sends Flow Control Frames when necessary. The MAC receiver interprets and processes incoming flow control frames. The Flow Control Frame Received counter is incremented whenever a flow control frame is received. When flow control is off: In full duplex mode, the MAC transmitter does not send flow control frames. The MAC receiver does not interpret or process the flow control frames. The Flow Control Frame Receiver counter is not incremented. Asymmetric Flow Control Enable. - 0 - Disable asymmetric flow control - 1 - Enable asymmetric flow control Bit [5] * * When this bit is set, and flow control is on (bit[0] = 0), don't send out a flow control frame. But MAC Receiver interprets and process flow control frames. (Default is 0) SS - Spanning tree state (802.1D spanning tree protocol). (Default 2'b11) 00 - Blocking: Frame is dropped 01 - Listening: Frame is dropped 10 - Learning: Frame is dropped. Source MAC address is learned. 11 - Forwarding: Frame is forwarded. Source MAC address is learned. Bit [7:6] 10.2.2 I2C ECR2Pn: Port N Control Register Address: 01+2n; Serial Interface Address:h001+2n (n=0to3) Accessed by serial interface (R/W) 7 6 5 3 2 DisL Ftf 1 0 Futf Security En Bit[0]: * * * * * * * * * * Filter untagged frame (Default 0) 0: Disable 1: Enable - All untagged frames from this port are discarded or follow security option when security is enable Filter Tag frame (Default 0) 0: Disable 1: Enable - All tagged frames from this port are discarded or follow security option when security is enable Learning Disable (Default 0) 0: Learning is enabled on this port 1: Learning is disabled on this port Reserved Bit[1]: Bit[2]: Bit [5:3] 36 Data Sheet Bit[7:6] * * MVTX2801 Security Enable (Default 00). The MVTX2801 checks the incoming data for one of the following conditions: If the source MAC address of the incoming packet is in the MAC table and is defined as secure address but the ingress port is not the same as the port associated with the MAC address in the MAC table. A MAC address is defined as secure when its entry at MAC table has static status and bit 0 is set to 1. MAC address bit 0 (the first bit transmitted) indicates whether the address is unicast or multicast. As source addresses are always unicast bit 0 is not used (always 0). MVTX2801 uses this bit to define secure MAC addresses. If the port is set as learning disable and the source MAC address of the incoming packet is not defined in the MAC address table. If the port is configured to filter untagged frames and an untagged frame arrives or if the port is configured to filter tagged frames and a tagged frame arrives. If one of these three conditions occurs, the packet will be handled according to one of the following specified options: 00 - Disable port security 01 - Enable port security. Port will be disabled when security violation is detected 10 - N/A 11 - N/A * * * * 10.2.3 GGControl 0- Extra GIGA Port Control Serial Interface Address:h012 Accessed by and serial interface (R/W) 7 6 5 MII1 4 Rst1 3 2 1 MII0 0 Rst0 Bit[0]: * Reset GIGA port 0 (Default is 0) - 0: Normal operation - 1: Reset Gigabit port 0. Bit[1]: * GIGA port 0 use MII interface (10/100M) (Default is 0) - 0: Gigabit port operation at 1000M mode - 1: Gigabit port operation at 10/100M mode (MII) Bit[3:2]: Bit[4]: * * Reserved -Must be '0' (Default 0) Reset GIGA port 1 (Default 0) - 0: Normal operation - 1: Reset Gigabit port 1. Bit[5]: * GIGA port 1 use MII interface (10/100M) (Default 0) - 0: Gigabit port operation at 1000M mode - 1: Gigabit port operation at 10/100M mode (MII) Bit[7:6]: * Reserved - Must be '0' (Default 0) 37 MVTX2801 10.2.4 GGControl 1- Extra GIGA Port Control Serial Interface Address:h013 Accessed by CPU and serial interface (R/W) 7 6 5 MII3 4 Rst3 3 2 1 MII2 0 Rst2 Data Sheet Bit[0]: * Reset GIGA port 2 Default is 0 - 0: Normal operation - 1: Reset Gigabit port 2 Bit[1]: * GIGA port 2 use MII interface (10/100M) Default is 0 - 0: Gigabit port operation at 1000M mode - 1: Gigabit port operation at 10/100M mode (MII) Bit[3:2]: Bit[3]: Bit[4]: * * * Reserved - Must be '0' (Default '0') Reserved - Must be '0' Reset GIGA port 3 Default is 0 - 0: Normal operation - 1: Reset Gigabit port 3. Bit[5]: * GIGA port 3 use MII interface (10/100M) Default is 0 - 0: Gigabit port operation at 1000M mode - 1: Gigabit port operation at 10/100M mode (MII) Bit[7:6]: * Reserved - Must be '0' (Default '0') 10.3 10.3.1 Group 1 Address - VLAN Group AVTCL - VLAN Type Code Register Low I2C Address h12; Serial Interface Address:h100 Accessed by serial interface and I2C (R/W) Bit[7:0]: * VLANType_LOW: Lower 8 bits of the VLAN type code (Default 00) 38 Data Sheet 10.3.2 2 MVTX2801 AVTCH - VLAN Type Code Register High I C Address h13; Serial Interface Address:h101 Accessed by serial interface and I2C (R/W) Bit [7:0] * VLANType_HIGH: Upper 8 bits of the VLAN type code (Default is 81) 10.3.3 PVMAP00_0 - Port 00 Configuration Register 0 I2C Address h14, Serial Interface Address:h102) Accessed by serial interface and I2C (R/W) Port Based VLAN Mode This register indicates the legal egress ports. Example: A "1" on bit 3 means that packets arriving on port 0 can be sent to port 3. A "0" on bit 3 means that any packet destined to port 3 will be discarded. Bit[3:0]: * VLAN Mask for ports 3 to 0 (Default F) - 0 - Disable - 1 - Enable Bit[7:4]: * Reserve (Default F) 10.3.4 I2C P PVMAP00_3 - Port 00 Configuration Register 3 Address h17, Serial Interface Address:h105 Accessed by serial interface and I2C (R/W) Port Based Mode 7 FP en 6 Drop 5 Default TX priority 3 2 FNT 1 Reserved 0 Bit [1:0]: Bit [2]: * * Reserved (Default 0) Force untagout (Default 0) - 0 Disable - 1 Force untag output All packets transmitted from this port are untagged. This register is used when this port is connected to legacy equipment that does not support VLAN tagging. 39 MVTX2801 Bit [5:3]: * Fixed Transmit priority. Used when bit[7] = 1 (Default 0) 000 Transmit Priority Level 0 (Lowest) 001 Transmit Priority Level 1 010 Transmit Priority Level 2 011 Transmit Priority Level 3 100 Transmit Priority Level 4 101 Transmit Priority Level 5 110 Transmit Priority Level 6 111 Transmit Priority Level 7 (Highest) Data Sheet Bit [6]: * Fixed Discard priority (Default 0) - 0 - Discard Priority Level 0 (Lowest) - 1 - Discard Priority Level 7(Highest) Bit [7]: * Enable Fix Priority (Default 0) - 0 Disable fix priority. All frames are analysed. Transmit Priority and Drop Priority are based on VLAN Tag, TOS or Logical Port. - 1 Transmit Priority and Discard Priority are based on values programmed in bit [6:3] Port VLAN Map PVMAP00_0,3 I2C Address h14, 17; Serial Interface Address:h102, 105) See above format PVMAP01_0,3 I2C Address h18, 1B; Serial Interface Address:h106, 109) See above format PVMAP02_0,3 I2C Address h1C, 1F; Serial Interface Address:h10A, 10D) See above format PVMAP03_0,3 I2C Address h20,23; Serial Interface Address:h10E, 111) See above format 10.3.5 PVMODE I2C Address: h038, Serial Interface Address:h126 Accessed by serial interface (R/W) 7 6 MP 5 BPDU 4 DM 3 Reserved 0 Bit [3:0]: Bit [4]: * * Reserved - Must be '0' Disable MAC address 0 - 0: MAC address 0 is not leaned. - 1: MAC address 0 is leaned. 40 Data Sheet Bit [5]: * Force BPDU as multicast frame (Default 0) MVTX2801 - 1: Enable. BPDU frames (frames with destination MAC address in the range of 01-80-C2 00-00-00 through 01-80-C2-00-00-0F) are forwarded as multicast frames. - 0: Disable. Drop frames in this range. Bit [6]: * MAC/PORT - 0: Single MAC address per system - 1: Single MAC address per port Bit [7]: * Reserved 10.4 10.4.1 Group 2 Address - Port Trunking Group TRUNK0_MODE - Trunk group 0 and 1 mode I2C Address: h039, Serial Interface Address:h207 Accessed by serial interface and I2C (R/W) Port Selection in unmanaged mode. Trunk group 0 and trunk group 1 are enable accordingly to bit [1:0] when input pin P_d[9] = 0 (external pull down). 7 2 1 Port sel 0 Bit [1:0]: * Port member selection for Trunk 0 and 1 in unmanaged mode (Default 2'b00) 00 - Only trunk group 0 is enable. Port 0 and 1 are used for trunk group0 01 - Only trunk group 0 is enable. Port 0,1 and 2 are used for trunk group0 10 - Only trunk group 0 is enable. Port 0,1,2 and 3 are used for trunk group0 11 - Trunk group 0 and 1 are enable. Port 0, 1 used for trunk group0, and port 2 and 3 are used for trunk group1 10.4.2 2 TX_AGE - Tx Queue Aging timer I C Address: h03B;Serial Interface Address:h312 Accessed by serial interface and I2C (R/W) 7 6 5 Tx Queue Agent Bit[4:0]: Bit[5]: Bit[7:6]: * * * Unit of 100ms (Default 8). Disable transmission queue aging if value is zero. Must be set to '0' Reserved 0 41 MVTX2801 10.5 10.5.1 Group 4 Address - Search Engine Group AGETIME_LOW - MAC address aging time Low Data Sheet I2C Address h03C; Serial Interface Address:h400 Accessed by serial interface and I2C (R/W) Bit [7:0] Low byte of the MAC address aging timer. (Default 2c) Mac address aging is enable/disable by boot strap T_d[9]. 10.5.2 I2C AGETIME_HIGH -MAC address aging time High Address h03D; Serial Interface Address h401 Accessed by serial interface and I2C (R/W) Bit [7:0]: High byte of the MAC address aging timer. (Default 00) Aging time is based on the following equation: {AGETIME_HIGH,AGETIME_LOW} X (# of MAC entries X100sec) Note: the number of entries= 66K when T_d[5] is pull down (SRAM memory size = 512K) and 34K when T_d[5] is pull up (SRAM memory size = 256K). 10.5.3 SE_OPMODE - Search Engine Operation Mode Serial Interface Address:h403 Accessed by CPU (R/W) 7 SL 6 DMS 5 0 Bit [5:0]: Bit [6]: * * Reserved Disable MCT speed-up aging (Default 0) - 1 - Disable speed-up aging when MCT resource is low. - 0 - Enable speed-up aging when MCT resource is low. Bit [7]: * Slow Learning (Default 0) - 1- Enable slow learning. Learning is temporary disabled when search demand is high - 0 - Learning is performed independent of search demand 42 Data Sheet 10.6 10.6.1 2 MVTX2801 Group 5 Address - Buffer Control/QOS Group FCBAT - FCB Aging Timer I C Address h03E; Serial Interface Address:h500 7 FCBAT 0 Bit [7:0]: * * FCB Aging time. Unit of 1ms. (Default FF) FCBAT define the aging time out interval of FCB handle 10.6.2 QOSC - QOS Control I2C Address h03F; Serial Interface Address:h501 Accessed by serial interface and I2C (R/W) 7 Tos-d 6 Tos-p 5 4 VF1c 3 1 fb 0 Bit [0]: Bit [4]: * * QoS frame lost is OK. Priority will be available for flow control enabled source only when this bit is set (Default 0) Per VLAN (Port based) Multicast Flow Control (Default 0) - 0 - Disable - 1 - Enable Bit [5]: Bit [6]: * * Reserved Select TOS bits for Priority (Default 0) - 0 - Use TOS [4:2] bits to map the transmit priority - 1 - Use TOS [5:3] bits to map the transmit priority Bit [7]: * select TOS bits for Drop (Default 0) - 0 - Use TOS [4:2] bits to map the drop priority - 1 - Use TOS [5:3] bits to map the drop priority 43 MVTX2801 10.6.3 FCR - Flooding Control Register I2C Address h040; Serial Interface Address:h502 Accessed by serial interface and I2C (R/W) 7 Tos 6 TimeBase 4 3 U2MR 0 Data Sheet Bit [3:0]: * U2MR: Unicast to Multicast Rate. Units in terms of time base defined in bits [6:4]. This is used to limit the amount of flooding traffic. The value in U2MR specifies how many packets are allowed to flood within the time specified by bit [6:4]. To disable this function, program U2MR to 0. (Default = 4'h8) TimeBase: (Default = 000) 000 = 10us 001 = 20us 010 = 40us 011 = 80us 100 = 160us 101 = 320us 110 = 640us 111 = 10us, same as 000. Bit [6:4]: * Bit [7]: * Select VLAN tag or TOS field (IP packets) to be preferentially picked to map transmit priority and drop priority (Default = 0). - 0 - Select VLAN tag priority field over TOS field - 1 - Select TOS field over VLAN tag priority field 10.6.4 I2C AVPML - VLAN Priority Map Address h041; Serial Interface Address:h503 Accessed by serial interface and I2C (R/W) 7 6 VP2 5 VP1 3 2 VP0 0 Registers AVPML, AVPMM, and AVPMH allow the eight VLAN priorities to map into eight internal level transmit priorities. Under the internal transmit priority, "seven" is the highest priority where as "zero" is the lowest. This feature allows the user the flexibility of redefining the VLAN priority field. For example, programming a value of 7 into bit 2:0 of the AVPML register would map packet VLAN priority) into internal transmit priority 7. The new priority is used only inside the 2801. When the packet goes out it carries the original priority. Bit [2:0]: Bit [5:3]: Bit [7:6]: * * * Mapped priority of 0 (Default 000) Mapped priority of 1 (Default 001) Mapped priority of 2 (Default 10) 44 Data Sheet 10.6.5 2 MVTX2801 AVPMM - VLAN Priority Map I C Address h042, Serial Interface Address:h504 Accessed by serial interface and I2C (R/W) 7 VP5 6 VP4 4 3 VP3 1 0 VP2 Map VLAN priority into eight level transmit priorities: Bit [0]: Bit [3:1]: Bit [6:4]: Bit [7]: * * * * Mapped priority of 2 (Default 0) Mapped priority of 3 (Default 011) Mapped priority of 4 (Default 100) Mapped priority of 5 (Default 1) 10.6.6 I2C AVPMH - VLAN Priority Map Address h043, Serial Interface Address:h505 Accessed by serial interface and I2C (R/W) 7 VP7 5 4 VP6 2 1 0 VP5 Map VLAN priority into eight level transmit priorities: Bit [1:0]: Bit [4:2]: Bit [7:5]: * * * Mapped priority of 5 (Default 10) Mapped priority of 6 (Default 110) Mapped priority of 7 (Default 111) 10.6.7 TOSPML - TOS Priority Map I2C Address h044, Serial Interface Address:h506 Accessed by serial interface and I2C (R/W) 7 TP2 6 5 TP1 3 2 0 TP0 Map TOS field in IP packet into four level transmit priorities Bit [2:0]: Bit [5:3]: Bit [7:6]: * * * Mapped priority when TOS is 0 (Default 000) Mapped priority when TOS is 1 (Default 001) Mapped priority when TOS is 2 (Default 10) 45 MVTX2801 10.6.8 TOSPMM - TOS Priority Map I2C Address h045, Serial Interface Address:h507 Accessed by serial interface and I2C (R/W) 7 TP5 6 TP4 4 3 TP3 1 TP2 0 Data Sheet Map TOS field in IP packet into four level transmit priorities Bit [0]: Bit [3:1]: Bit [6:4]: Bit [7]: * * * * Mapped priority when TOS is 2 (Default 0) Mapped priority when TOS is 3 (Default 011) Mapped priority when TOS is 4 (Default 100) Mapped priority when TOS is 5 (Default 1) 10.6.9 I2C TOSPMH - TOS Priority Map Address h046, Serial Interface Address:h508 Accessed by serial interface and I2C (R/W) 7 TP7 5 4 TP6 2 1 TP5 0 Map TOS field in IP packet into four level transmit priorities: Bit [1:0]: Bit [4:2]: Bit [7:5]: * * * Mapped priority when TOS is 5 (Default 01) Mapped priority when TOS is 6 (Default 110) Mapped priority when TOS is 7 (Default 111) 10.6.10 AVDM - VLAN Discard Map I2C Address h047, Serial Interface Address:h509 Accessed by serial interface and I2C (R/W) 7 FDV7 6 FDV6 5 FDV5 4 FDV4 3 FDV3 2 FDV2 1 FDV1 0 FDV0 Map VLAN priority into frame discard when low priority buffer usage is above threshold. Frames with high discard (drop) priority will be discarded (dropped) before frames with low drop priority. - 0 - Low discard priority - 1 - High discard priority 46 Data Sheet Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: * * * * * * * * MVTX2801 Frame discard priority for frames with VLAN transmit priority 0 (Default 0) Frame discard priority for frames with VLAN transmit priority 1 (Default 0) Frame discard priority for frames with VLAN transmit priority 2 (Default 0) Frame discard priority for frames with VLAN transmit priority 3 (Default 0) Frame discard priority for frames with VLAN transmit priority 4 (Default 0) Frame discard priority for frames with VLAN transmit priority 5 (Default 0) Frame discard priority for frames with VLAN transmit priority 6 (Default 0) Frame discard priority for frames with VLAN transmit priority 7 (Default 0) 10.6.11 TOSDML - TOS Discard Map I2C Address h048, Serial Interface Address:h50A Accessed by serial interface and I2C (R/W) 7 FDT7 6 FDT6 5 FDT5 4 FDT4 3 FDT3 2 FDT2 1 FDT1 0 FDT0 Map TOS into frame discard when low priority buffer usage is above threshold Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: * * * * * * * * Frame discard priority for frames with TOS transmit priority 0 (Default 0) Frame discard priority for frames with TOS transmit priority 1 (Default 0) Frame discard priority for frames with TOS transmit priority 2 (Default 0) Frame discard priority for frames with TOS transmit priority 3 (Default 0) Frame discard priority for frames with TOS transmit priority 4 (Default 0) Frame discard priority for frames with TOS transmit priority 5 (Default 0) Frame discard priority for frames with TOS transmit priority 6 (Default 0) Frame discard priority for frames with TOS transmit priority 7 (Default 0) 10.6.12 BMRC - Broadcast/Multicast Rate Control I2C Address h049, Serial Interface Address:h50B Accessed by serial interface and I2C (R/W) 7 Broadcast Rate 4 3 Multicast Rate 0 This broadcast and multicast rate defines for each port the number of incoming packet allowed to be forwarded within a specified time. Once the packet rate is reached, packets will be dropped. To turn off the rate limit, program the field to 0. 47 MVTX2801 Bit [3:0]: Bit [7:4]: * * Data Sheet Multicast Rate Control Number of multicast packets allowed within the time defined in bits 6 to 4 of the Flooding Control Register (FCR). (Default 0). Broadcast Rate Control Number of broadcast packets allowed within the time defined in bits 6 to 4 of the Flooding Control Register (FCR). (Default 0) 10.6.13 UCC - Unicast Congestion Control I2C Address h04A, Serial Interface Address:h50C Accessed by serial interface and I2C (R/W) 7 Unicast congest threshold 0 Bit [7:0]: * Number of frame count. Used for best effort dropping at B% when destination port's best effort queue reaches UCC threshold and shared pool is all in use. Granularity 16 frame. (Default: h07) 10.6.14 MCC - Multicast Congestion Control I2C Address h0B7, Serial Interface Address:h50D Accessed by serial interface and I2C (R/W) 7 FC reaction prd 5 4 3 0 Multicast congest threshold Bit [3:0]: Bit [4]: Bit [7:5]: * * * In multiples of two. Used for triggering MC flow control when destination port's best effort queue reaches MCC threshold. (Default 5'h08) Must be 0 Flow control reaction period. ([7:5] 4)+3 usec (Default 3'h2). 10.6.15 I2C PRG - Port Reservation for Giga ports Address h0B9, Serial Interface Address:h50F Accessed by serial interface and I2C (R/W) 7 Buffer low thd 4 3 0 Per source buffer Reservation 48 Data Sheet Bit [3:0]: * MVTX2801 Per source buffer reservation. Define the space in the FDB reserved for each port. Expressed in multiples of 16 packets. For each packet 1536 bytes are reserved in the memory. Default: 4'hA for 4MB memory 4'h6 for 2MB memory 4'h3 for 1MB memory Expressed in multiples of 16 packets. Threshold for dropping all best effort frames when destination port best effort queues reach UCC threshold and shared pool is all used and source port reservation is at or below the PRG[7:4] level. Also the threshold for initiating UC flow control. Default: 4'h6 for 4MB memory 4'h2 for 2MB memory 4'h1 for 1MB memory * Bits [7:4]: 49 MVTX2801 FCB Reservation Data Sheet 10.6.16 SFCB - Share FCB Size I2C Address h04E), Serial Interface Address:h510 Accessed by serial interface and I2C (R/W) 7 Shared buffer size 0 Bits [7:0]: * Expressed in multiples of 8. Buffer reservation for shared pool. (Default (Default (Default (Default (Default (Default 4G 4G 4G 8G 8G 8G & & & & & & 4M 2M 1M 4M 2M 1M = = = = = = 8'd62) 8'd20) 8'd08) 8'd150) 8'd55) 8'd25) 10.6.17 C2RS - Class 2 Reserved Size I2C Address h04F, Serial Interface Address:h511 Accessed by serial interface and I2C (R/W) 7 Class 2 FCB Reservation 0 Bits [7:0]: * Buffer reservation for class 2 (third lowest priority). Granularity 2. (Default 8'h00) 10.6.18 I2C C3RS - Class 3 Reserved Size Address h050, Serial Interface Address:h512 Accessed by serial interface and I2C (R/W) 7 Class 3 FCB Reservation 0 Bits [7:0]: * Buffer reservation for class 3. Granularity 2. (Default 8'h00) 50 Data Sheet 10.6.19 2 MVTX2801 C4RS - Class 4 Reserved Size I C Address h051, Serial Interface Address:h513 Accessed by serial interface and I2C (R/W) 7 Class 4 FCB Reservation 0 Bits [7:0]: * Buffer reservation for class 4. Granularity 2. (Default 8'h00) 10.6.20 C5RS - Class 5 Reserved Size I2C Address h052; Serial Interface Address:h514 Accessed by serial interface and I2C (R/W) 7 Class 5 FCB Reservation 0 Bits [7:0]: * Buffer reservation for class 5. Granularity 2. (Default 8'h00) 10.6.21 I2C C6RS - Class 6 Reserved Size Address h053; Serial Interface Address:h515 Accessed by serial interface and I2C (R/W) 7 Class 6 FCB Reservation 0 Bits [7:0]: * Buffer reservation for class 6 (second highest priority). Granularity 2. (Default 8'h00) 10.6.22 C7RS - Class 7 Reserved Size I2C Address h054; Serial Interface Address:h516 Accessed by serial interface and I2C (R/W)` 7 Class 7 FCB Reservation 0 Bits [7:0]: * Buffer reservation for class 7 (highest priority). Granularity 2. (Default 8'h00) 51 MVTX2801 Classes Byte Gigabit Port 0 Data Sheet 10.6.23 QOSC00 - BYTE_C2_G0 I2C Address h055, Serial Interface Address:h517 Bits [7:0]: * Byte count threshold for C2 queue WRED (Default 8'h28) (1024byte/unit when Delay Bound is used) (1024byte/unit when WFQ is used) 10.6.24 QOSC01 - BYTE_C3_G0 I2C Address h056, Serial Interface Address:h518 Bits [7:0]: * Byte count threshold for C3 queue WRED (Default 8'h28) (512byte/unit when Delay Bound is used) (1024byte/unit when WFQ is used) 10.6.25 I2C QOSC02 - BYTE_C4_G0 Address h057, Serial Interface Address:h519 Bits [7:0]: * Byte count threshold for C4 queue WRED (Default 8'h28) (256byte/unit when Delay Bound is used) (1024byte/unit when WFQ is used) 10.6.26 I2C QOSC03 - BYTE_C5_G0 Address h058, Serial Interface Address:h51A Bits [7:0]: * Byte count threshold for C5 queue WRED (Default 8'h28) (128byte/unit when Delay Bound is used) (1024byte/unit when WFQ is used) 10.6.27 I2C QOSC04 - BYTE_C6_G0 Address h059, Serial Interface Address:h51B Bits [7:0]: * Byte count threshold for C6 queue WRED (Default 8'h50) (64byte/unit when Delay Bound is used) (1024byte/unit when WFQ is used) 10.6.28 QOSC05 - BYTE_C7_G0 I2C Address h05A, Serial Interface Address:h51C Bits [7:0]: * Byte count threshold for C6 queue WRED (Default 8'h50) (64byte/unit when Delay Bound is used) (1024byte/unit when WFQ is used) 52 Data Sheet MVTX2801 QOSC00 through QOSC05 represent the values F-A in Table 3 for Gigabit port 0. They are per-queue byte thresholds for weighted random early drop (WRED). QOSC05 represents A, and QOSC00 represents F. Classes Byte Gigabit Port 1 10.6.29 I2C QOSC06 - BYTE_C2_G1 Address h05B, Serial Interface Address:h51D Bits [7:0]: * Byte count threshold for C2 queue WRED (Default 8'h28) (1024byte/unit when Delay Bound is used) (1024byte/unit when WFQ is used) 10.6.30 QOSC07 - BYTE_C3_G1 I2C Address h05C, Serial Interface Address:h51E Bits [7:0] * Byte count threshold for C3 queue WRED (Default 8'h28) (512 byte/unit when Delay Bound is used) (1024 byte/unit when WFQ is used) 10.6.31 QOSC08 - BYTE_C4_G1 I2C Address h05D, Serial Interface Address:h51F Bits [7:0]: * Byte count threshold for C4 queue WRED (Default 8'h28) (256 byte/unit when Delay Bound is used) (1024byte/unit when WFQ is used) 10.6.32 2 QOSC09 - BYTE_C5_G1 I C Address h05E, Serial Interface Address:h520 Bits [7:0]: * Byte count threshold for C5 queue WRED (Default 8'h28) (128 byte/unit when Delay Bound is used) (1024 byte/unit when WFQ is used) 10.6.33 I2C QOSC0A - BYTE_C6_G1 Address h05F, Serial Interface Address:h521 Bits [7:0]: * Byte count threshold for C6 queue WRED (Default 8'h50) (64 byte/unit when Delay Bound is used) (1024 byte/unit when WFQ is used) 53 MVTX2801 10.6.34 QOSC0B - BYTE_C7_G1 I2C Address h060, Serial Interface Address:h522 Bits [7:0]: * Byte count threshold for C7 queue WRED (Default 8'h50) (64 byte/unit when Delay Bound is used) (1024 byte/unit when WFQ is used) Data Sheet QOSC06 through QOSC0B represent the values F-A in Table 3. They are per-queue byte thresholds for random early drop. QOSC0B represents A, and QOSC06 represents F. Classes Byte Gigabit Port 2 10.6.35 2 QOSC0C - BYTE_C2_G2 I C Address h061, Serial Interface Address:h523 Bits [7:0]: * Byte count threshold for C2 queue WRED (Default 8'h28) (1024 byte/unit when Delay Bound is used) (1024 byte/unit when WFQ is used) 10.6.36 QOSC0D - BYTE_C3_G2 I2C Address h062, Serial Interface Address:h524 Bits [7:0]: * Byte count threshold for C3 queue WRED (Default 8'h28) (512 byte/unit when Delay Bound is used) (1024 byte/unit when WFQ is used) 10.6.37 QOSC0E - BYTE_C4_G2 I2C Address h063, Serial Interface Address:h525 Bits [7:0]: * Byte count threshold for C4 queue WRED (Default 8'h28) (256 byte/unit when Delay Bound is used) (1024 byte/unit when WFQ is used) 10.6.38 2 QOSC0F - BYTE_C5_G2 I C Address h064, Serial Interface Address:h526 Bits [7:0]: * Byte count threshold for C5 queue WRED (Default 8'h28) (128 byte/unit when Delay Bound is used) (1024 byte/unit when WFQ is used) 54 Data Sheet 10.6.39 2 MVTX2801 QOSC10 - BYTE_C6_G2 I C Address h065, Serial Interface Address:h527 Bits [7:0]: * Byte count threshold for C6 queue WRED (Default 8'h50) (64 byte/unit when Delay Bound is used) (1024 byte/unit when WFQ is used) 10.6.40 2 QOSC11 - BYTE_C7_G2 I C Address h066, Serial Interface Address:h528 Bits [7:0]: * Byte count threshold for C7 queue WRED (Default 8'h50) (64 byte/unit when Delay Bound is used) (1024 byte/unit when WFQ is used) QOSC0C through QOSC11 represent the values F-A in Table 3 for Gigabit port 2. They are per-queue byte thresholds for random early drop. QOSC11 represents A, and QOSC0C represents F. Classes Byte Gigabit Port 3 10.6.41 I2C QOSC12 - BYTE_C2_G3 Address h067, Serial Interface Address:h529 Bits [7:0]: * Byte count threshold for C2 queue WRED (Default 8'h28) (1024 byte/unit when Delay Bound is used) (1024 byte/unit when WFQ is used) 10.6.42 I2C QOSC13 - BYTE_C3_G3 Address h068, Serial Interface Address:h52A Bits [7:0]: * Byte count threshold for C3 queue WRED (Default 8'h28) (512 byte/unit when Delay Bound is used) (1024 byte/unit when WFQ is used) 10.6.43 2 QOSC14 - BYTE_C4_G3 I C Address h069, Serial Interface Address:h52B Bits [7:0]: * Byte count threshold for C4 queue WRED (Default 8'h28) (256 byte/unit when Delay Bound is used) (1024 byte/unit when WFQ is used) 10.6.44 QOSC15 - BYTE_C5_G3 I2C Address h06A, Serial Interface Address:h52C Bits [7:0]: * Byte count threshold for C5 queue WRED (Default 8'h28) (128 byte/unit when Delay Bound is used) (1024 byte/unit when WFQ is used) 55 MVTX2801 10.6.45 QOSC16 - BYTE_C6_G3 I2C Address h06B, Serial Interface Address:h52D Bits [7:0]: * Byte count threshold for C6 queue WRED (Default 8'h50) (64 byte/unit when Delay Bound is used) (1024 byte/unit when WFQ is used) Data Sheet 10.6.46 QOSC17 - BYTE_C7_G3 I2C Address h06C, Serial Interface Address:h52E Bits [7:0]: * Byte count threshold for C7 queue WRED (Default 8'h50) (64 byte/unit when Delay Bound is used) (1024 byte/unit when WFQ is used) QOSC12 through QOSC17 represent the values F-A in Table 3 for Gigabit port 3. They are per-queue byte thresholds for random early drop. QOSC17 represents A, and QOSC12 represents F. Classes WFQ Credit Set 0 10.6.47 QOSC33 - CREDIT_C0_G0 Serial Interface Address:h54A Bits [5:0]: Bits [7:6]: * W0 - Credit register for WFQ. (Default 6'h04) 00: Option 1 01: Option 2 10: Option 3 11: Option 4 Priority type. Define one of the four QoS mode of operation for port 0 (Default 2'00) See table below: Queue Option 1 Bit [7:6] = 2'B00 Option 2 Bit [7:6] = 2'B01 Option 3 Bit [7:6] = 2'B10 Option 4 Bit [7:6] = 2'B11 Credit for WFQ - Bit [5:0] P7 P6 P5 P4 P3 P2 P1 BE BE P0 DELAY BOUND SP SP WFQ W7 W6 W5 W4 W3 W2 DELAY BOUND WFQ W1 W0 10.6.48 QOSC34 - CREDIT_C1_G0 Serial Interface Address:h54B Bits [7]: * Flow control allow during WFQ scheme. (Default 1'b1) 0 = Not support QoS when the Source port Flow control status is on. 1= Always support QoS) 56 Data Sheet Bits [6]: * Flow control BE Queue only. (Default 1'b1) 0= DO NOT send any frames if the XOFF is on. 1= the P7-P2 frames can be sent even the XOFF is ON W1 - Credit register. (Default 4'h04) Lost_ok Ingress- for src fc status 0 1 0 1 0 1 MVTX2801 Bits [5:0] Fc_allow * Fc_be_only Egress- for dest fc_status 0 0 1 1 X X 0 0 0 0 1 1 Go to BE Queue if (Src FC or Des FC on) otherwise Normal Go to BE Queue if (Dest FC on) otherwise Normal (WFQ only) Go to BE Queue if (Src FC on) otherwise BAD (WFQ only) Always Normal Go to BE Queue if (Src FC on) Always Normal 10.6.49 QOSC35 - CREDIT_C2_G0 Serial Interface Address:h54C Bits [5:0] Bits [7:6]: * * W2 - Credit register. (Default 4'h04) Reserved 10.6.50 QOSC36 - CREDIT_C3_G0 Serial Interface Address:h54D Bits [5:0] Bits [7:6]: * * W3 - Credit register. (Default 4'h04) Reserved 10.6.51 QOSC37 - CREDIT_C4_G0 Serial Interface Address:h54E Bits [5:0] Bits [7:6]: * * W4 - Credit register. (Default 4'h04) Reserved 10.6.52 QOSC38 - CREDIT_C5_G0 Serial Interface Address:h54F Bits [5:0] Bits [7:6]: * * W5 - Credit register. (Default 5'h8) Reserved 57 MVTX2801 10.6.53 QOSC39- CREDIT_C6_G0 Serial Interface Address:h550 Bits [5:0] Bits [7:6]: * * W6 - Credit register. (Default 5'h8) Reserved Data Sheet 10.6.54 QOSC3A- CREDIT_C7_G0 Serial Interface Address:h551 Bits [5:0] Bits [7:6]: * * W7 - Credit register. (Default 5'h10) Reserved QOSC33 through QOSC3Arepresents the set of WFQ parameters (see section 7.5) for Gigabit port 0. The granularity of the numbers (bits [5:0]) is 1, and their sum must be 64. QOSC33 corresponds to W0, and QOSC3A corresponds to W7. Classes WFQ Credit Port G1 10.6.55 QOSC3B - CREDIT_C0_G1 Serial Interface Address:h552 Bits [5:0]: Bits [7:6]: * W0 - Credit register for WFQ. (Default 6'h04) 00: Option 1 01: Option 2 10: Option 3 11: Option 4 Priority type. Define one of the four QoS mode of operation for port 1 (Default 2'00) See table below: Queue Option 1 Bit [7:6] = 2'B00 Option 2 Bit [7:6] = 2'B01 Option 3 Bit [7:6] = 2'B10 Option 4 Bit [7:6] = 2'B11 Credit for WFQ - Bit [5:0] P7 P6 P5 P4 P3 P2 P1 BE BE P0 DELAY BOUND SP SP WFQ W7 W6 W5 W4 W3 W2 DELAY BOUND WFQ W1 W0 10.6.56 QOSC3C - CREDIT_C1_G1 Serial Interface Address:h54B Bits [7]: * Flow control allow during WFQ scheme. (Default 1'b1) 0 = Not support QoS when the Source port Flow control status is on. 1= Always support QoS) 58 Data Sheet Bits [6]: * Flow control BE Queue only. (Default 1'b1) 0= DO NOT send any frames if the XOFF is on. 1= the P7-P2 frames can be sent even the XOFF is ON W1 - Credit register. (Default 4'h04) Lost_ok Ingress- for src fc status 0 1 0 1 0 1 MVTX2801 Bits [5:0] Fc_allow * Fc_be_only Egress- for dest fc_status 0 0 1 1 X X 0 0 0 0 1 1 Go to BE Queue if (Src FC or Des FC on) otherwise Normal Go to BE Queue if (Dest FC on) otherwise Normal (WFQ only) Go to BE Queue if (Src FC on) otherwise BAD (WFQ only) Always Normal Go to BE Queue if (Src FC on) Always Normal 10.6.57 QOSC3D - CREDIT_C2_G1 Serial Interface Address:h553 Bits [5:0] Bits [7:6]: * * W2 - Credit register. (Default 4'h04) Reserved 10.6.58 QOSC3E - CREDIT_C3_G1 Serial Interface Address:h554 Bits [5:0] Bits [7:6]: * * W3 - Credit register. (Default 4'h04) Reserved 10.6.59 QOSC3F - CREDIT_C4_G1 Serial Interface Address:h555 Bits [5:0] Bits [7:6]: * * W4 - Credit register. (Default 4'h04) Reserved 10.6.60 QOSC40 - CREDIT_C5_G1 Serial Interface Address:h556 Bits [5:0] Bits [7:6]: * * W5 - Credit register. (Default 5'h8) Reserved 59 MVTX2801 10.6.61 QOSC41- CREDIT_C6_G1 Serial Interface Address:h557 Bits [5:0] Bits [7:6]: * * W6 - Credit register. (Default 5'h8) Reserved Data Sheet 10.6.62 QOSC42- CREDIT_C7_G1 Serial Interface Address:h558 Bits [5:0] Bits [7:6]: * * W7 - Credit register. (Default 5'h10) Reserved QOSC3B through QOSC42 represents the set of WFQ parameters (see section 7.5) for Gigabit port 1. The granularity of the numbers (bits [5:0]) is 1, and their sum must be 64. QOSC3B corresponds to W0, and QOSC42 corresponds to W7. Classes WFQ Credit Port G2 10.6.63 QOSC43 - CREDIT_C0_G2 Serial Interface Address:h55A Bits [5:0]: Bits [7:6]: * * W0 - Credit register for WFQ. (Default 6'h04) Priority type. Define one of the four QoS mode of operation for port 2 (Default 2'00) 00: Option 1 01: Option 2 10: Option 3 11: Option 4 See table below: Queue Option 1 Bit [7:6] = 2'B00 Option 2 Bit [7:6] = 2'B01 Option 3 Bit [7:6] = 2'B10 Option 4 Bit [7:6] = 2'B11 Credit for WFQ - Bit [5:0] P7 P6 P5 P4 P3 P2 P1 BE BE P0 DELAY BOUND SP SP WFQ W7 W6 W5 W4 W3 W2 DELAY BOUND WFQ W1 W0 10.6.64 QOSC44 - CREDIT_C1_G2 Serial Interface Address:h55B Bits [7]: * Flow control allow during WFQ scheme. (Default 1'b1) 0 = Not support QoS when the Source port Flow control status is on. 1= Always support QoS) 60 Data Sheet Bits [6]: * Flow control BE Queue only. (Default 1'b1) 0= DO NOT send any frames if the XOFF is on. 1= the P7-P2 frames can be sent even the XOFF is ON W1 - Credit register. (Default 4'h04) Lost_ok Ingress- for src fc status 0 1 0 1 0 1 MVTX2801 Bits [5:0] Fc_allow * Fc_be_only Egress- for dest fc_status 0 0 1 x X X 0 0 0 0 1 1 Go to BE Queue if (Src FC or Des FC on) otherwise Normal Go to BE Queue if (Dest FC on) otherwise Normal (WFQ only) Go to BE Queue if (Src FC on) otherwise BAD (WFQ only) Always Normal Go to BE Queue if (Src FC on) Always Normal 10.6.65 QOSC45 - CREDIT_C2_G2 Serial Interface Address:h55C Bits [5:0] Bits [7:6]: * * W2 - Credit register. (Default 4'h04) Reserved 10.6.66 QOSC46 - CREDIT_C3_G2 Serial Interface Address:h55D Bits [5:0] Bits [7:6]: * * W3 - Credit register. (Default 4'h04) Reserved 10.6.67 QOSC47 - CREDIT_C4_G2 Serial Interface Address:h55E Bits [5:0] Bits [7:6]: * * W4 - Credit register. (Default 4'h04) Reserved 10.6.68 QOSC48 - CREDIT_C5_G2 Serial Interface Address:h55F Bits [5:0] Bits [7:6]: * * W5 - Credit register. (Default 5'h8) Reserved 61 MVTX2801 10.6.69 QOSC49- CREDIT_C6_G2 Serial Interface Address:h560 Bits [5:0] Bits [7:6]: * * W6 - Credit register. (Default 5'h8) Reserved Data Sheet 10.6.70 QOSC4A- CREDIT_C7_G2 Serial Interface Address:h561 Bits [5:0] Bits [7:6]: * * W7 - Credit register. (Default 5'h10) Reserved QOSC43 through QOSC4Arepresents the set of WFQ parameters (see section 7.5) for Gigabit port 2. The granularity of the numbers (bits [5:0]) is 1, and their sum must be 64. QOSC43 corresponds to W0, and QOSC4A corresponds to W7. Classes WFQ Credit Port G3 10.6.71 QOSC4B - CREDIT_C0_G3 Serial Interface Address:h562 Bits [5:0]: Bits [7:6]: * * W0 - Credit register for WFQ. (Default 6'h04) Priority type. Define one of the four QoS mode of operation for port 3 (Default 2'00) 00: Option 1 01: Option 2 10: Option 3 11: Option 4 See table below: Queue Option 1 Bit [7:6] = 2'B00 Option 2 Bit [7:6] = 2'B01 Option 3 Bit [7:6] = 2'B10 Option 4 Bit [7:6] = 2'B11 Credit for WFQ - Bit [5:0] P7 P6 P5 P4 P3 P2 P1 BE BE P0 DELAY BOUND SP SP WFQ W7 W6 W5 W4 W3 W2 DELAY BOUND WFQ W1 W0 62 Data Sheet 10.6.72 QOSC4 - CREDIT_C1_G3 Serial Interface Address:h563 Bits [7]: * MVTX2801 Flow control allow during WFQ scheme. (Default 1'b1) 0 = Not support QoS when the Source port Flow control status is on. 1= Always support QoS) Flow control BE Queue only. (Default 1'b1) (0= DO NOT send any frames if the XOFF is on. (1= the P7-P2 frames can be sent even the XOFF is ON) W1 - Credit register. (Default 4'h04) Bits [6]: * Bits [5:0] * Fc_allow Fc_be_only Lost_ok Ingress- for src fc status 0 1 0 1 0 1 Go to BE Queue if (Src FC or Des FC on) otherwise Normal Go to BE Queue if (Dest FC on) otherwise Normal (WFQ only) Go to BE Queue if (Src FC on) otherwise BAD (WFQ only) Always Normal Go to BE Queue if (Src FC on) Always Normal Egress- for dest fc_status 0 0 1 1 X X 1 0 0 0 0 1 10.6.73 QOSC4D - CREDIT_C2_G3 Serial Interface Address:h564 Bits [5:0] Bits [7:6]: * * W2 - Credit register. (Default 4'h04) Reserved 10.6.74 QOSC4E - CREDIT_C3_G3 Serial Interface Address:h565 Bits [5:0] Bits [7:6]: * * W3 - Credit register. (Default 4'h04) Reserved 10.6.75 QOSC4F - CREDIT_C4_G3 Serial Interface Address:h566 Bits [5:0] Bits [7:6]: * * W4 - Credit register. (Default 4'h04) Reserved 63 MVTX2801 10.6.76 QOSC50 - CREDIT_C5_G3 Serial Interface Address:h567 Bits [5:0] Bits [7:6]: * * W5 - Credit register. (Default 5'h8) Reserved Data Sheet 10.6.77 QOSC51- CREDIT_C6_G3 Serial Interface Address:h568 Bits [5:0] Bits [7:6]: * * W6 - Credit register. (Default 5'h8) Reserved 10.6.78 QOSC52- CREDIT_C7_G3 Serial Interface Address:h569 Bits [5:0] Bits [7:6]: * * W7 - Credit register. (Default 5'h10) Reserved QOSC4B through QOSC52 represents the set of WFQ parameters (see section 7.5) for Gigabit port 3. The granularity of the numbers (bits [5:0]) is 1, and their sum must be 64. QOSC4B corresponds to W0, and QOSC52 corresponds to W7. Class 6 Shaper Control Port G0 10.6.79 QOSC73 - TOKEN_RATE_G0 Serial Interface Address:h58A Bits [7:0] * Bytes allow to transmit every frame time (0.512usec) when regulated by Shaper logic. (Default: 8'h08) 10.6.80 QOSC74 - TOKEN_LIMIT_G0 Serial Interface Address:h58B Bits [7:0] * Bytes allow to continue transmit out when regulated by Shaper logic. (16byte/unit) (Default: 8'hC0) QOSC73 and QOSC74 correspond to parameters from section 7.6 on the shaper for EF traffic. QOSC73 is an integer less than 64, with granularity 1. QOSC74 is the programmed maximum value of the counter (maximum burst size). This value is expressed in multiples of 16. QOSC73 and QOSC74 apply to Gigabit port 0. Register QOSC39-CREDIT_C6_G0 programs the peak rate. See QoS application note for more information. 64 Data Sheet Class 6 Shaper Control Port G1 MVTX2801 10.6.81 QOSC75 - TOKEN_RATE_G1 Serial Interface Address:h58C Bits [7:0] * Bytes allow to transmit every frame time (0.512usec) when regulated by Shaper logic. (Default: 8'h08) 10.6.82 QOSC76 - TOKEN_LIMIT_G1 Serial Interface Address:h58D Bits [7:0] * Bytes allow to continue transmit out when regulated by Shaper logic. (16byte/unit) (Default: 8'hC0) QOSC75 and QOSC76 correspond to parameters from section 7.6 on the shaper for EF traffic. QOSC75 is an integer less than 64, with granularity 1. QOSC76 is the programmed maximum value of the counter (maximum burst size). This value is expressed in multiples of 16. QOSC75 and QOSC76 apply to Gigabit port 1. Register QOSC41-CREDIT_C6_G1 programs the peak rate. See QoS application note for more information. Class 6 Shaper Control Port G2 10.6.83 QOSC77 - TOKEN_RATE_G2 Serial Interface Address:h58E Bits [7:0] * Bytes allow to transmit every frame time (0.512usec) when regulated by Shaper logic. (Default: 8'h08) 10.6.84 QOSC78 - TOKEN_LIMIT_G2 Serial Interface Address:h58F Bits [7:0] * Bytes allow to continue transmit out when regulated by Shaper logic. (16byte/unit) (Default: 8'hC0) QOSC77 and QOSC78 correspond to parameters from section 7.6 on the shaper for EF traffic. QOSC77 is an integer less than 64, with granularity 1. QOSC78 is the programmed maximum value of the counter (maximum burst size). This value is expressed in multiples of 16. QOSC77 and QOSC78 apply to Gigabit port 2. Register QOSC49-CREDIT_C6_G2 programs the peak rate. See QoS application note for more information. Class 6 Shaper Control Port G3 10.6.85 QOSC79 - TOKEN_RATE_G3 Serial Interface Address:h590 Bits [7:0] * Bytes allow to transmit every frame time (0.512usec) when regulated by Shaper logic. (Default: 8'h08) 65 MVTX2801 10.6.86 QOSC7A - TOKEN_LIMIT_G3 Serial Interface Address:h591 Bits [7:0] * * Data Sheet Bytes allow to to continue transmit out when regulated by Shaper logic. (16byte/unit) (Default: 8'hC0) QOSC79 and QOSC7A correspond to parameters from section 7.6 on the shaper for EF traffic. QOSC79 is an integer less than 64, with granularity 1. QOSC7A is the programmed maximum value of the counter (maximum burst size). This value is expressed in multiples of 16. QOSC79 and QOSC7A apply to Gigabit port 3. Register QOSC51-CREDIT_C6_G3 programs the peak rate. See QoS application note for more information. 10.6.87 RDRC0 - WRED Rate Control 0 I2C Address 085, Serial Interface Address:h59A Accessed by Serial Interface and I2C (R/W) 7 X Rate Bits [7:4]: Bits[3:0]: * * 4 3 Y Rate Corresponds to the percentage X% in Chapter 7. Used for random early drop. Granularity 6.25%. (Default: 4'h8) Corresponds to the percentage Y% in Chapter 7. Used for random early drop. Granularity 6.25%.(Default: 4'hE) 0 10.6.88 RDRC1 - WRED Rate Control 1 I2C Address 086, Serial Interface Address:h59B Accessed by Serial Interface and I2C (R/W) 7 Z Rate 4 3 B Rate 0 Bits [7:4]: Bits[3:0]: * * Corresponds to the percentage Z% in Chapter 7. Used for random early drop. Granularity 6.25%.%. (Default: 4'h6) Corresponds to the best effort frame drop percentage B%, when shared pool is all in use and destination port best effort queue reaches UCC. Used for random early drop. Granularity 6.25%.%. (Default: 4'h8) 66 Data Sheet 10.7 10.7.1 2 MVTX2801 Group 6 Address - MISC Group MII_OP0 - MII Register Option 0 I C Address h0B1, Serial Interface Address:h600 Accessed by serial interface and I2C (R/W) 7 Hfc 6 1prst 5 NP 4 Vendor Spc. Reg Addr 0 Bit [7]: * Half duplex flow control no default enable (Do not use half duplex mode) - 0 = Half duplex flow control always enable - 1 = Half duplex flow control by negotiation Bit[6]: Bit [5] * * Link partner reset auto-negotiate disable Next page enable - 1: enable - 0: disable Bit[4:0]: * Vendor specified link status register address (null value means don't use it) (Default 00) 10.7.2 I2C MII_OP1 - MII Register Option 1 Address 0B2, Serial Interface Address:h601 Accessed by serial interface and I2C (R/W) 7 Speed bit location 4 3 Duplex bit location 0 Bits[3:0]: Bits [7:4]: * * Duplex bit location in vendor specified register Speed bit location in vendor specified register (Default 00) 67 MVTX2801 10.7.3 FEN - Feature Register I2C Address h0B3, Serial Interface Address:h602 Accessed by serial interface and I2C (R/W) 7 DML 6 MII 5 3 DS 2 1 0 Data Sheet Bits [1:0]: Bit [2]: * * Reserved Support DS EF Code. (Default 0) - 0 - Disable - 1 - Enable (all ports) * Bit [5:3]: Bit [6]: Bit [7]: * When 101110 is detected in DS field (TOS[7:2]), the frame priority is set for 110 and drop is set for 0. Reserved - 0: Enable MII Management State Machine (Default 0) - 1: Disable MII Management State Machine - 0: Enable using MCT Link List structure - 1: Disable using MCT Link List structure 10.7.4 MIIC0 - MII Command Register 0 Serial Interface Address:h603 Accessed by serial interface (R/W) Bit [7:0] MII Data [7:0] Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY, and no VALID; then program MII command. 10.7.5 MIIC1 - MII Command Register 1 Serial Interface Address:h604 Accessed by serial interface (R/W) Bit [7:0] * MII Data [15:8] Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command. 68 Data Sheet 10.7.6 MIIC2 - MII Command Register 2 Serial Interface Address:h605 Accessed by serial interface (R/W) 7 6 MII OP 5 4 Register address 0 MVTX2801 Bits [4:0]: Bit [6:5] * * REG_AD - Register PHY Address OP - Operation code "10" for read command and "01" for write command Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command. 10.7.7 MIIC3 - MII Command Register 3 Serial Interface Address:h606 Accessed by serial interface (R/W) 7 Rdy 6 Valid 5 4 PHY address 0 Bits [4:0]: Bit [6] Bit [7] * * * PHY_AD - 5 Bit PHY Address VALID - Data Valid from PHY (Read Only) RDY - Data is returned from PHY (Ready Only) Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command. 10.7.8 MIID0 - MII Data Register 0 Serial Interface Address:h607 Accessed by serial interface (RO) Bit [7:0] * MII Data [7:0] 10.7.9 MIID1 - MII Data Register 0 Serial Interface Address:h608 Accessed by serial interface (RO) Bit [7:0] * MII Data [15:8] 69 MVTX2801 10.7.10 LED Mode - LED Control I2C Address:h0B4; Serial Interface Address:h609 Accessed by serial interface and I2C (R/W) 7 lpbk 6 5 Out Pattern 4 3 Clock rate 2 1 Hold Time 0 Data Sheet Bit[1:0] * Sample hold time (Default 2'b00) 2'b00- 8 msec 2'b01- 16 msec 2'b10- 32 msec 2'b11- 64 msec Bit[3:2] * LED clock speed (serial mode) (Default 2'b10) 2'b00- sclk/128 2'b01- sclk/256 2'b10- sclk/1024 2'b11- sclk/2048 LED clock speed (parallel mode) (Default 2'b10) 2'b00- sclk/1024 2'b01- sclk/4096 2'b10- sclk/2048 2'b11- sclk/8192 Bit[5:4] LED indicator out pattern (Default 2'b11) 2'b00- Normal output, LED signals go straight out, no logical combination 2'b01- 4 bi-color LED mode 2'b10- 3 bi-color LED mode 2'b11- programmable mode Normal mode: LED_BYTEOUT_[7]:Collision (COL) LED_BYTEOUT_[6]:Full duplex (FDX) LED_BYTEOUT_[5]:Speed[1] (SP1) LED_BYTEOUT_[4]:Speed[0] (SP0) LED_BYTEOUT_[3]:Link (LNK) LED_BYTEOUT_[2]:Rx (RXD) LED_BYTEOUT_[1]:Tx (TXD) 70 Data Sheet Bit[5:4] cont'd LED_BYTEOUT_[0]:Flow Control (FC) 4 bi-color LED mode LED_BYTEOUT_[7]:COL LED_BYTEOUT_[6]:1000FDX LED_BYTEOUT_[5]:1000HDX LED_BYTEOUT_[4]:100FDX LED_BYTEOUT_[3]:100HDX LED_BYTEOUT_[2]:10FDX LED_BYTEOUT_[1]:10HDX LED_BYTEOUT_[0]:ACT Note: All output qualified by Link signal 3 bi-color LED mode: LED_BYTEOUT_[7]:COL LED_BYTEOUT_[6]:LNK LED_BYTEOUT_[5]:FC LED_BYTEOUT_[4]:SPD1000 LED_BYTEOUT_[3]:SPD100 LED_BYTEOUT_[2]:FDX LED_BYTEOUT_[1]:HDX LED_BYTEOUT_[0]:ACT Note: All output qualified by Link signal Programmable mode: LED_BYTEOUT_[7]:Link MVTX2801 LED_BYTEOUT_[6:0]:Defined by the LEDSIG6 ~ LEDSIG0 programmable registers. Note: All output qualified by Link signal Bit[6]: Bit[7]: * * Reserved. Must be '0' Enable internal loop back. When this bit is set to '1' all ports work in internal loop back mode. For normal operation must be '0'. 71 MVTX2801 10.7.11 CHECKSUM - EEPROM Checksum I2C Address h0C5, Serial Interface Address:h60B Accessed by serial interface and I2C (R/W) Bit [7:0]: * * Data Sheet (Default 00) Before requesting that the MVTX2801 updates the EEPROM device, the correct checksum needs to be calculated and written into this checksum register. The checksum formula is: FF i2C register = 0 i=0 After booting cycle the MVTX2801 calculates the checksum. If the checksum is not zeroed the MVTX2801 does not start. 10.7.12 10.7.13 I2C LED User LEDUSER0 Address h0BB, Serial Interface Address:h60C Accessed by serial interface and I2C (R/W) 7 LED USER0 0 Bit [7:0]: * (Default 00) Content will send out by LED serial logic 10.7.14 I2C LEDUSER1 Address h0BC, Serial Interface Address:h60D Accessed by serial interface and I2C (R/W) 7 LED USER1 0 Bit [7:0]: * (Default 00) Content will send out by LED serial logic 72 Data Sheet 10.7.15 2 MVTX2801 LEDUSER2/LEDSIG2 I C Address h0BD, Serial Interface Address:h60E Accessed by serial interface and I2C (R/W) In serial mode: 7 LED USER2 0 Bit [7:0]: * (Default 00) Content will be sent out by LED serial shift logic In parallel mode: this register is used for programming the LED pin - led_byteout_[2] 7 COL FDX SP1 4 SP0 3 COL FDX SP1 0 SP0 Bit [3:0]: (Default 4'H0) Signal polarity: 0: not invert polarity (high true) 1: invert polarity (Default 4'H8) Signal Select: 0: not select 1: select the corresponding bit When bits get selected, the led_byteout_[2] = AND (all selected bits) Bit [7:4] 73 MVTX2801 10.7.16 LEDUSER3/LEDSIG3 I2C Address:h0BE, Serial Interface Address:h60F Access by CPU, serial interface (R/W) In serial mode: 7 LED USER3 0 Data Sheet Bit [7:0]: * (Default 8'H33) Content will be sent out by LED serial shift logic. In parallel mode: this register is used for programming the LED pin - led_byteout_[3] 7 COL FDX SP1 4 SP0 3 COL FDX SP1 0 SP0 Bit [3:0]: (Default 4'H3) Signal polarity: 0: not invert polarity (high true) 1: invert polarity (Default 4'H3) Signal Select: 0: not select 1: select the corresponding bit When bits get selected, the led_byteout_[3] = AND (all selected bits) Bit [7:4] 10.7.17 I2C LEDUSER4/LEDSIG4 Address:h0BF, Serial Interface Address:h610 Access by CPU, serial interface (R/W) 7 LED USER4 0 Bit [7:0] (Default 8'H32) Content will be sent out by LED serial shift logic. In parallel mode: this register is used for programming the LED pin - led_byteout_[4] 7 COL FDX SP1 4 SP0 3 COL FDX SP1 0 SP0 74 Data Sheet Bit [3:0] (Default 4'H2) Signal polarity: 0: not invert polarity (high true) 1: invert polarity (Default 4'H3) Signal Select 0: not select 1: select the corresponding bit MVTX2801 Bit [7:4] When bits get selected, the led_byteout_[4] = AND (all selected bits) 10.7.18 I2C LEDUSER5/LEDSIG5 Address:h0C0, Serial Interface Address:h611 Access by CPU, serial interface (R/W) 7 LED USER5 0 Bit [7:0] (Default 8'H20) Content will be sent out by LED serial shift logic. In parallel mode: this register is used for programming the LED pin - led_byteout_[5] 7 COL Bit [3:0] FDX SP1 4 SP0 3 COL FDX SP1 0 SP0 (Default 4'H0) Signal polarity: 0: not invert polarity (high true) 1: invert polarity (Default 4'H2) Signal Select: 0: not select 1: select the corresponding bit When bits get selected, the led_byteout_[5] = AND (all selected bits) Bit [7:4] 75 MVTX2801 10.7.19 LEDUSER6/LEDSIG6 I2C Address:h0C1, Serial Interface Address:h612 Access by CPU, serial interface (R/W) 7 LED USER6 0 Data Sheet Bit [7:0] (Default 8'H40) Content will be sent out by LED serial shift logic. In parallel mode: this register is used for programming the LED pin - led_byteout_[6] 7 COL Bit [3:0] FDX SP1 4 SP0 3 COL FDX SP1 0 SP0 (Default 4'B0000) Signal polarity: 0: not invert polarity (high true) 1: invert polarity (Default 4'b0100) Signal Select: 0: not select 1: select the corresponding bit When bits get selected, the led_byteout_[6] = AND (all selected bits), or the polarity of led_byteout_[6] is controlled by LEDSIG1_0[3] Bit [7:4] 10.7.20 I2C LEDUSER7/LEDSIG1_0 Address:h0C2, Serial Interface Address:h613 Access by CPU, serial interface (R/W) 7 LED USER7 (Default 8'H61) Content will be sent out by LED serial shift logic. In parallel mode: this register is used for programming the LED pin - led_byteout_[2] 7 GP RX TX 4 FC 3 P6 RX TX 0 FC Bit [7:0] 0 76 Data Sheet Bit [7] MVTX2801 (Default 1'B0) Global output polarity: this bit controls the output polarity of all led_byteout_ and led_port_sel pins. 0: no invert polarity - (led_byteout_[7:0] are high activated, led_port_sel[9:0] are low activated) 1: invert polarity - (led_byteout_[7:0] are low activated, led_port_sel[9:0] are high activated) (Default 3'B110) Signal Select 0: not select 1: select the corresponding bit When bits get selected, the led_byteout_[6] = OR (all selected bits) Bit [6:4] Bit[3] (Default 1'B0) Polarity control of led_byteout_[6] 0: not invert 1: invert (Default 3'b001) Signal Select: 0: not select 1: select the corresponding bit When bits get selected, the led_byteout_[0] = OR (all selected bits) Bit [2:0] 10.7.21 MIINP0 - MII Next Page Data Register 0 I2C Address:h0C3, Serial Interface Address:h614 Access by CPU and serial interface only (R/W) Bit [7:0] MII next page Data [7:0] 10.7.22 I2C MIINP1 - MII Next Page Data Register 1 Address:h0C4, Serial Interface Address:h615 Access by CPU and serial interface only (R/W) Bit [7:0] MII next page Data [15:8] 77 MVTX2801 10.8 10.8.1 Group F Address - CPU Access Group GCR-Global Control Register Data Sheet Serial Interface Address: hF00 Accessed by serial interface. (R/W) 7 4 3 Reset 2 Bist 1 SR 0 SC Bit [0]: Bit[1]: Bit[2]: * * * * * * * * * Store configuration (Default = 0) Write '1' followed by '0' to store configuration into external EEPROM Store configuration and reset (Default = 0) Write '1' to store configuration into external EEPROM and reset chip Start BIST (Default = 0) Write '1' followed by '0' to start the device's built-in self-test. The result is found in the DCR register. Soft Reset (Default = 0) Write '1' to reset the chip Reserved Bit[3]: Bit[7:4]: 10.8.2 DCR-Device Status and Signature Register Serial Interface Address: hF01 Accessed by serial interface. (RO) 7 Revision 6 5 Signature 4 RE 3 2 BinP 1 BR 0 BW Bit [0]: Bit[1]: Bit[2]: Bit[3]: Bit[5:4]: 1 - Busy writing configuration to I2C 0 - Not Busy writing configuration to I2C 1 - Busy reading configuration from I2C 0 - Not Busy reading configuration from I2C 1 - BIST in progress 0 - BIST not running 1 - RAM Error 0 - RAM OK Device Signature 00 - 4 Ports Device, non-management mode 01 - 8 Ports Device, non-management mode 10 - 4 Ports Device, management mode possible (need to install CPU) 11 - 8 Ports Device, management mode possible (need to install CPU) Revision Bit [7:6]: 78 Data Sheet 10.8.3 DCR01-Giga port status Serial Interface Address: hF02 Accessed by serial interface. (RO) 7 CIC 6 4 3 GIGA1 2 1 GIGA0 0 MVTX2801 Bit [1:0]: Giga port 0 strap option 00 - 100Mb MII mode 01 - Invalid 10 - GMII 11 - PCS Giga port 1 strap option 00 - 100Mb MII mode 01 - Invalid 10 - GMII 11 - PCS Chip initialization completed Note: DCR01[7], DCR23[7], DCR45[7] and DCR67[7] have the same function. Bit[3:2] Bit [7] 10.8.4 DCR23-Giga port status Serial Interface Address: hF03 Accessed by CPU and serial interface. (RO) 7 CIC 6 4 3 GIGA3 2 1 GIGA2 0 Bit [1:0]: Giga port 2 strap option 00 - 100Mb MII mode 01 - Invalid 10 - GMII 11 - PCS Giga port 3 strap option 00 - 100Mb MII mode 01 - Invalid 10 - GMII 11 - PCS Chip initialization completed Bit[3:2] Bit [7] 79 MVTX2801 10.8.5 DPST - Device Port Status Register Serial Interface Address:hF06 Accessed by CPU and serial interface (R/W) Bit[2:0]: Data Sheet Read back index register. This is used for selecting what to read back from DTST. (Default 00) 3'B000 - Port 0 Operating mode and Negotiation status 3'B001 - Port 1 Operating mode and Negotiation status 3'B010 - Port 2 Operating mode and Negotiation status 3'B011 - Port 3 Operating mode and Negotiation status 3'B1XX - Reserved 10.8.6 DTST - Data Read Back Register Serial Interface Address: hF07 Accessed by CPU and serial interface (RO) 7 MD 6 InfoDet 5 SigDet 4 Giga 3 Inkdn 2 FE 1 Fdpx 0 Fc_en This register provides various internal information as selected in DPST bit[2:0] Bit[0]: Bit[1]: Bit[2]: Bit[3]: Bit[4]: Bit[5]: Bit[6]: Bit[7]: Flow control enabled Full duplex port Fast ethernet port (if not giga) Link is down GIGA port Signal detect (when PCS interface mode) Pipe signal detected (pipe mode only) Module detected (for hot swap purpose) 80 Data Sheet 11.0 11.1 MVTX2801 BGA and Ball Signal Description BGA Views (Top View) 1 D 2 3 N EN 4 NC NC 5 NC NC NC NC 6 NC NC NC NC NC 7 NC NC NC NC NC 8 NC NC NC NC NC 9 NC NC NC NC NC 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC S_CL K NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC B_A[1 B_A[1 B_A[7 B_A[2 B_OE B_D[ B_D[ NC4 NC3 6] 2] ] ] # 27] 26] B_A[1 B_A[1 B_A[8 B_A[3 B_W B_D[ DEV_ NC5 B_D[25 7] 3] ] ] E# 30] CFG[ ] B_A[1 B_A[1 B_A[1 B_A[5 B_A[4 B_D[ 8] 4] 1] ] ] 28] NC B_A[9 B_A[1 B_AD NC2 B_D[ ] 0] SC# 29] AVD B_CL B_D[22 D K ] B_D[ B_D[ B_D[21 24] 18] ] A AVD NC9 SCA B DEV_ LA_D NC7 CF[0] [0] C LA_D LA_C LA_D NC6 [1] [2] [8] [10] [15] [20] [23] [28] L LK [5] [7] [11] [16] [21] [25] [30] [3] [9] [6] [12] [19] [22] [26] [4] [13] [18] [29] [27] D LA_D LA_D LA_D NC8 E LA_D LA_D LA_D LA_D AGN D VDD VDD VD33 VD33 VD33 VSS VSS VD33 VD33 VD33 [14] [17] [24] [31] [33] LB_A[ B_A[1 B_A[6 B_D[ AGN B_D[ B_D[ B_D[ B_D[ B_D[14 20] 5] ] 31] D 17] 23] 19] 16] ] VDD VDD VSS VSS NC1 B_D[ B_D[ B_D[ B_D[12 9] 10] 11] ] VDD B_D[ B_D[ B_D[ B_D[ B_D[7] 20] 4] 3] 6] B_D[ B_D[ P_IN B_D[ B_D[2] 15] 8] T# 1] VDD B_D[ P_A[1 P_A[2 P_W P_RD# 13] ] ] E# VDD B_D[ P_D[ P_D[ P_D[ P_D[13 5] 15] 11] 12] ] P_CS P_D[ P_D[ P_D[ P_D[10 # 14] 7] 8] ] VD33 P_A[ B_D[ P_D[ P_D[ P_D[5] 0] 0] 3] 4] F LA_D LA_D LA_D LA_D LA_D VSS VSS G LA_D LA_D LA_D LA_D LA_D VDD H LA_D LA_D LA_D LA_D LA_D J LA_D LA_D LA_D LA_D LA_D VDD K LA_D LA_D LA_C LA_D LA_D VDD S0# [37] LA_C LA_R LA_D LA_D LA_D S1# W# [32] [46] [41] M LA_D LA_D LA_D LA_D LA_D VD33 [34] [38] [43] [49] [58] [63] 6] 10] 15] 19] [35] [40] [44] [50] [57] [62] 5] 9] 13] 17] [36] [42] [45] [51] [55] [60] 3] 8] 12] 16] [53] [61] 4] [52] [54] [59] 14] 20] [48] VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS [56] [39] [47] [7] [11] [18] XD[1] N LA_D LA_D LA_D LA_D LA_D VD33 P LA_D LA_D LA_D LA_A[ LA_D VD33 R LA_D LA_D LA_D LA_D LA_D VSS T LA_D LA_D LA_D LA_D LA_A VSS U LA_D LA_D LA_D LA_D LA_A VD33 V LA_A[ LA_A[ LA_A[ LA_A[ LA_A VD33 W LA_A[ LA_A[ LA_A[ LA_A[ G0_T VD33 Y LA_A[ LA_A[ LA_A[ G0_C G0_T VD33 P_D[ P_D[ P_D[ P_D[ P_D[2] 6] 9] 0] 1] VD33 T_D[ T_D[1 T_D[1 T_D[1 T_D[14 15] 1] 2] 3] ] VSS T_D[ T_D[5 T_D[7 T_D[8 T_D[9] 10] ] ] ] VSS T_D[ T_D[4 T_D[2 T_D[1 T_D[0] 6] ] ] ] VD33 S_RS T_D[3 TMO TMO RESO T# ] DE[1] DE[0] UT# VD33 NC[7] G7_R LESY LE_C LE_DO X ER NO# LK0 VD33 NC[3] NC[1] G7_R NC[6] NC[5] X DV NC[6] G7_T NC[4] NC[2] NC[0] X EN VDD NC[0] NC[3] G7_C G7_R MIITX OL XCLK CK[7] VDD NC[7] G7_T NC[7] NC[5] NC[4] X ER NC[2] NC[4] NC[2] NC[1] G7_CR S/L VDD NC[0] NC G7_T NC XCLK NC RS/L XD[4] FC[0] XD[7] A A LA_A[ LA_A[ LA_A[ GRE G0_T VDD A B MIITX G0_T G0_T G0_T G0_T VDD CK[0] XD[2] XD[0] XCLK X ER A C G0_R G0_T G0_T G0_R G0_R XCLK XD[5] XD[3] XD[2] XD[6] A D G0_R G0_T G0_C G0_T G0_R VSS XD[0] X EN OL XD[6] X DV VDD VDD VD33 VD33 VD33 VSS VSS VD33 VD33 VD33 VDD VDD A E G0_R G0_R G0_R G0_R G1_T VSS VDD VSS VSS NC[7] NC[6] NC[5] NC[3] NC[1] NC[5] NC NC[6] NC NC NC[5] XD[5] XD[4] XD[3] XD[1] XD[0] A F G0_R G0_R GRE G1_R G1_R G1_R G2_T G2_T G2_R G2_R G2_R G3_T G3_T G3_C G3_R G3_R IND_ G3_R G3_R NC[3] NC[1] NC[4] NC[2] NC[4] NC XD[7] X ER FC[1] XD[2] XD[5] XD[7] XD[0] XD[7] XD[2] XD[4] XD[5] XD[1] XD[6] OL XD[3] XD[6] CM XD[4] X ER M_M NC[1] NC[5] NC[6] NC[7] NC DIO NC[4] NC[6] NC NC NC NC NC NC[5] MIITX NC[1] NC[3] NC[4] NC CK[5] NC[3] NC A G G1_T G1_T G1C G1_T G2_T G1_R G2_T G2_T G2_R G2_R G2_R G2_R G3_T G3_R G3_R G3_R NC XD[1] XCLK RS/L XD[7] XCLK XD[4] XD[4] XD[3] XD[3] XCLK XD[7] X ER X EN XD[0] XD[5] XD[7] A H G1_T G1_T MIITX G1_R G1_R G2C MIITX G2_T G2_R G2_R G3_T G3_T G3_T G3_R G3_R G3_R NC NC[3] NC[6] NC[1] NC[2] NC NC[4] NC NC[7] NC NC NC[0] XD[2] XD[3] CK[1] XD[0] XCLK RS/L CK[2] X EN XD[1] X DV XCLK XD[3] XD[5] XCLK XD[2] X DV A J G1_T G1_T G1_T G1_C G1_R GRE G2_T G2_T G2_R G2_R GRE G3_T MIITX G3_T G3_R M_M NC[0] NC[5] NC[7] NC[0] NC NC[0] NC[6] NC[0] NC NC[1] NC[7] NC[2] NC XD[5] XD[4] X ER OL XD[6] FC[2] XD[2] XD[6] XD[0] XD[6] FC[3] XD[2] CK[3] X ER XD[1] DC NC[2] NC[3] NC RS/L XD[0] XD[4] XD[7] CLK RS/L CK[4] MIITX NC CK[6] A K G1_T G1_T G1_R G1_R G1_R G1_R G2_T G2_T G2_T G2_C G3_C G3_T G3_T G3_T CM_ G4C NC[2] MIITX NC XD[6] X EN XD[1] XD[3] X DV X ER XD[1] XD[5] X ER OL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 81 MVTX2801 11.2 Power and Ground Distribution Data Sheet 1 2 3 4 NC NC 5 NC NC NC NC 6 NC NC NC NC NC 7 NC NC NC NC NC 8 NC NC NC NC NC 9 NC NC NC NC NC 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC S_CL K NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC B_A[ B_A[ B_A[ B_A[ B_OE B_D[ B_D[ NC4 NC3 16] 12] 7] 2] # 27] 26] B_A[ B_A[ B_A[ B_A[ B_W B_D[ DEV_ NC5 B_D[ 17] 13] 8] 3] E# 30] CFG[ 25] B_A[ B_A[ B_A[ 18] 14] 11] NC B_A[ B_A[ 9] 10] B_A[ B_A[ B_D[ AVD B_CL B_D[ 5] 4] 28] D K 22] B_AD NC2 B_D[ B_D[ B_D[ B_D[ SC# 29] 24] 18] 21] A AVDD NC9 SCA N EN B DEV_C LA_D NC7 F[0] [0] C LA_D[1 LA_C LA_D NC6 ] LK [3] D LA_D[2 LA_D LA_D NC8 ] [5] [9] E LA_D[8 LA_D LA_D LA_D[ AGN ] [7] [6] 4] D LB_A B_A[ B_A[ B_D[ AGN B_D[ B_D[ B_D[ B_D[ B_D[ [20] 15] 6] 31] D 17] 23] 19] 16] 14] VDD VDD VSS VSS NC1 B_D[ B_D[ B_D[ B_D[ 9] 10] 11] 12] VDD B_D[ B_D[ B_D[ B_D[ B_D[ 20] 4] 3] 6] 7] B_D[ B_D[ P_IN B_D[ B_D[ 15] 8] T# 1] 2] VDD B_D[ P_A[ P_A[ P_W P_RD 13] 1] 2] E# # VDD B_D[ P_D[ P_D[ P_D[ P_D[ 5] 15] 11] 12] 13] P_CS P_D[ P_D[ P_D[ P_D[ # 14] 7] 8] 10] VD33 P_A[ B_D[ P_D[ P_D[ P_D[ 0] 0] 3] 4] 5] F LA_D[1 LA_D LA_D LA_D[ LA_D VSS VSS 0] [11] [12] 13] [14] G LA_D[1 LA_D LA_D LA_D[ LA_D VDD 5] [16] [19] 18] [17] H LA_D[2 LA_D LA_D LA_D[ LA_D 0] [21] [22] 29] [24] J LA_D[2 LA_D LA_D LA_D[ LA_D VDD 3] [25] [26] 27] [31] K LA_D[2 LA_D LA_C LA_D[ LA_D VDD 8] [30] S0# 37] [33] L LA_CS LA_R LA_D LA_D[ LA_D 1# W# [32] 46] [41] M LA_D[3 LA_D LA_D LA_D[ LA_D VD33 4] [35] [36] 53] [48] N LA_D[3 LA_D LA_D LA_D[ LA_D VD33 8] [40] [42] 61] [56] P LA_D[4 LA_D LA_D LA_A[ LA_D VD33 3] [44] [45] 4] [39] R LA_D[4 LA_D LA_D LA_D[ LA_D VSS 9] [50] [51] 52] [47] T LA_D[5 LA_D LA_D LA_D[ LA_A VSS 8] [57] [55] 54] [7] U LA_D[6 LA_D LA_D LA_D[ LA_A VD33 3] [62] [60] 59] [11] V LA_A[6 LA_A LA_A LA_A[ LA_A VD33 ] [5] [3] 14] [18] W LA_A[1 LA_A LA_A LA_A[ G0_T VD33 0] [9] [8] 20] XD[1] Y LA_A[1 LA_A LA_A G0_C G0_T 5] [13] [12] RS/L XD[4] AA LA_A[1 LA_A LA_A GREF G0_T VDD 9] [17] [16] C[0] XD[7] AB MIITX G0_T G0_T G0_T G0_T VDD CK[0] XD[2] XD[0] XCLK X ER AC G0_RX G0_T G0_T G0_R G0_R CLK XD[5] XD[3] XD[2] XD[6] AD G0_RX G0_T G0_C G0_T G0_R VSS D[0] X EN OL XD[6] X DV AE G0_RX G0_R G0_R G0_R G1_T VSS VDD D[5] XD[4] XD[3] XD[1] XD[0] VDD VDD VD33 VD33 VD33 VSS VSS VD33 VD33 VD33 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VD33 P_D[ P_D[ P_D[ P_D[ P_D[ 6] 9] 0] 1] 2] VD33 T_D[ T_D[ T_D[ T_D[ T_D[ 15] 11] 12] 13] 14] VSS T_D[ T_D[ T_D[ T_D[ T_D[ 10] 5] 7] 8] 9] VSS T_D[ T_D[ T_D[ T_D[ T_D[ 6] 4] 2] 1] 0] VD33 S_RS T_D[ TMO TMO RES T# 3] DE[1] DE[0] OUT# VD33 NC[7] G7_R LESY LE_C LE_D X ER NO# LK0 O VD33 NC[3] NC[1] G7_R NC[6] NC[5] X DV NC[6] G7_T NC[4] NC[2] NC[0] X EN VDD NC[0] NC[3] G7_C G7_R MIITX OL XCLK CK[7] VDD NC[7] G7_T NC[7] NC[5] NC[4] X ER NC[2] NC[4] NC[2] NC[1] G7_C RS/L VDD NC[0] NC G7_T NC XCLK NC VDD VDD VD33 VD33 VD33 VSS VSS VD33 VD33 VD33 VDD VDD VSS VSS NC[7] NC[6] NC[5] NC[3] NC[1] NC[5] NC NC[6] NC NC NC[5] AF G0_RX G0_R GRE G1_R G1_R G1_R G2_T G2_T G2_R G2_R G2_R G3_T G3_T G3_C G3_R G3_R IND_ G3_R G3_R NC[3] NC[1] NC[4] NC[2] NC[4] NC D[7] X ER FC[1] XD[2] XD[5] XD[7] XD[0] XD[7] XD[2] XD[4] XD[5] XD[1] XD[6] OL XD[3] XD[6] CM XD[4] X ER AG G1_TX G1_T G1C G1_T G2_T G1_R G2_T G2_T G2_R G2_R G2_R G2_R G3_T G3_R G3_R G3_R NC D[1] XCLK RS/L XD[7] XCLK XD[4] XD[4] XD[3] XD[3] XCLK XD[7] X ER X EN XD[0] XD[5] XD[7] AH G1_TX G1_T MIITX G1_R G1_R G2C MIITX G2_T G2_R G2_R G3_T G3_T G3_T G3_R G3_R G3_R NC D[2] XD[3] CK[1] XD[0] XCLK RS/L CK[2] X EN XD[1] X DV XCLK XD[3] XD[5] XCLK XD[2] X DV M_M NC[1] NC[5] NC[6] NC[7] NC DIO NC[4] NC[6] NC NC NC NC NC NC[5] MIITX NC[1] NC[3] NC[4] NC CK[5] NC[3] NC NC[3] NC[6] NC[1] NC[2] NC NC[4] NC NC[7] NC NC NC[0] AJ G1_TX G1_T G1_T G1_C G1_R GRE G2_T G2_T G2_R G2_R GRE G3_T MIITX G3_T G3_R M_M NC[0] NC[5] NC[7] NC[0] NC D[5] XD[4] X ER OL XD[6] FC[2] XD[2] XD[6] XD[0] XD[6] FC[3] XD[2] CK[3] X ER XD[1] DC AK G1_TX G1_T G1_R G1_R G1_R G1_R G2_T G2_T G2_T G2_C G3_C G3_T G3_T G3_T CM_ G4C NC[2] MIITX NC D[6] X EN XD[1] XD[3] X DV X ER XD[1] XD[5] X ER OL RS/L XD[0] XD[4] XD[7] CLK RS/L CK[4] NC[0] NC[6] NC[0] NC NC[1] NC[7] NC[2] NC NC[2] NC[3] NC MIITX NC CK[6] 82 Data Sheet 11.3 Ball- Signal Descriptions MVTX2801 All pins are CMOS type; all Input pins are 5 Volt tolerance, and all Output pins are 3.3 CMOS drive. Ball No(s) K27, L27, K30, K29, K28 L30 Symbol P_DATA[15:11] P_DATA[10] I/O I/O-TS with pull up I/O - TS with pull up Description Not used - leave unconnected Trunk enable External pull up or unconnecteddisable trunk group 0 and 1 External pull down - enable trunk group 0 and 1 See register TRUNK0_MODE for port selection and trunk enable. Trunk enable External pull up or unconnected disable trunk group 2 and 3 External pull down - enable trunk group 2 and 3 See register TRUNK1_MODE for port selection and trunk enable. Bootstrap function - See bootstrap section Not used - leave unconnected Not used - leave unconnected I2C Data Clock I2C Data I/O N27 P_DATA[9] I/O - TS with pull up L29, L28, N26, M30, M29, M28, N30, N29, N28 J28 H28 P_DATA[8:0] P_A[2] P_INT# I/O - TS with pull up Input Output I2C Interface (0) Note: In unmanaged mode, Use I2C and Serial control interface to configure the system J27 M26 Serial Control Interface J29 L26 J30 Frame Buffer Interface U1, U2, N4, U3, U4, T1, T2, N5, T3, T4, M4, R4, R3, R2, R1, M5, R5, L4, P3, P2, P1, N3, L5, N2, P5, N1, K4, M3, M2, M1, K5, L3, J5, K2, H4, K1, J4, J3, J2, H5, J1, H3, H2, H1, G3, G4, G5, G2, G1, F5, F4, F3, F2, F1, D3, E1, E2, E3, D2., E4, C3, D1, C1, B2 AA1, V5, AA2, AA3, Y1, V4, Y2, Y3, U5, W1, W2, W3, T5, V1, V2, P4, V3 W4 C2 K3 L1 L2 LA_D[63:0] I/O-TS with pull up Frame Bank A- Data Bit [63:0] PS_STROBE PS_DO PS_DI (AUTOFD) Input with weak internal pull up Input with weak internal pull up Output with pull up Serial Strobe Pin Serial Data Input Serial Data Output (AutoFD) SCL SDA Output I/O-TS with pull up LA_A[19:3] Output Frame Bank A - Address Bit [19:3] LA_A[20] LA_CLK LA_CS0# LA_CS1# LA_RW# Output with pull up Output Output with pull up Output with pull up Output with pull up Frame Bank A - Address Bit [20] Frame Bank A Clock Input Frame Bank A Low Portion Chip Selection Frame Bank A High Portion Chip Selection Frame Bank A Read/Write Table 7 - Ball- Signal Descriptions 83 MVTX2801 Ball No(s) D18, B18, C18, A17, E17, B17, C17, E16, D17, B16, E15, C16, D16, D15, E14, C15, B15, E13, A15, D14, C14, D13, B14, A14, C13, E12, B13, A13, D12, C12, B12, A12, A11, E10, C10, B10, E9, A10, D11, D10, D8, D9, C9, B9, A9, C8, B8, A8, C7, E7, D7, B7, E8, A7, D6, C6, E6, B6, A6, A5, B5, C5, B4,A4 D22, D20, E20, D21, A21, D19, B21, C21, A20, B20, E19, C20, A19, B19, E18, C19, A18 F D5 B11 E11 C11 Switch Database Interface E24,B27, D27, C27, A27, A28, B30, D28, E27, C30, D30, G26, E28, D29, E26, E29, H26, E30, J26, F30, F29, F28, F27, H27, G30, G29, K26, G27, G28, H30, H29, M27 C22, B22, A22, E22, C23, B23, A23, C24, D24, D23, B24, A24, E23, C25, C26, B25, A25 C29 D25 B26 A26 MII Management Interface AJ16 AG18 M_MDC M_MDIO Output I/O-TS with pull up B_D[31:0] I/O-TS with pull up NC Symbol I/O I/O-TS with pull up. No Connect Data Sheet Description NC Output LB_A[20] NC NC NC NC Output with pull up Output Output with pull up Output with pull up Output with pull up Bootstrap Pin Switch Database Domain - Data Bit [31:0] B_A[18:2] Output Switch Database Address (512K) - Address Bit [18:2] B_CLK B_ADSC# B_WE# B_OE# Output Output with pull up Output with pull up Output with pull up Switch Database Clock Input Switch Database Address Status Control Switch Database Write Chip Select Switch Database Read Chip Select MII Management Data Clock (common for all MII Ports [3:0]) MII Management Data I/O (common for all MII Ports -[3:0])) 2.5Mhz GMII / MII Interface (193) Gigabit Ethernet Access Port AJ11, AJ6, AF3,AA4 AD29, AK30, AJ22, AG17 AK15 AF17 AJ13, AH7, AH3, AB1 AA30, AK29, AG25, AK18, GREF_CLK [3:0] NC CM_CLK IND/CM MII TX CLK[3:0] NC Input w/ pull up Input w/ pull up Input w/ pull up Common Clock shared by port G[3:0] 1: select GREF_CLK[3:0] as clock 0: select CM_CLK as clock for all ports Input w/ pull up Gigabit Reference Clock Table 7 - Ball- Signal Descriptions (continued) 84 Data Sheet Ball No(s) AG16, AF16, AG15, AF18, AF15, AH15, AJ15, AG14 AG11, AJ10, AF11, AF10, AG9, AF9, AH9, AJ9 AF6, AJ5, AF5, AG6, AK4, AF4, AK3, AH4 AF1, AC5, AE1, AE2, AE3, AC4, AE4, AD1 Symbol G3_RXD[7:0] G2_RXD[7:0] G1_RXD[7:0] G0_RXD[7:0] I/O Input w/ pull up MVTX2801 Description G[3:0] port - Receive Data Bit [7:0] V26, W29, W30, Y28, W26, NC Y29, W27, Y30 AB26, AE27, AE28, AC27, AE29, AC26, AE30, AD26 AK27, AH27, AF26, AJ27, AH26, AK25, AG26, AJ25 AG22, AG21, AG20, AF22, AK21, AK20, AF21, AJ20 AH16, AH10, AK5, AD5 W28, AD30, AK28, AH22, AF19, AG12, AK6, AF2 V27, AD27, AJ28, AH23, AK11, AH6, AG3, Y4 AC30, AJ29, AG23, AK16, AF14, AK10, AJ4, AD3 AA28, AF29, AJ26, AJ21, AH14, AG10, AH5, AC1 AA29, AF27, AK26, AH21, G[3:0]_RX_ER NC G[3:0]_CRS/LINK NC G[3:0]_COL NC G[3:0]_RXCLK NC Output G[3:0]port - Transmit Data Bit [7:0] Input w/ pull up G[3:0]port - Receive Clock Input w/ pull up G[3:0]port - Collision Detected Input w/ pull down G[3:0]port - Carrier Sense Input w/ pull up G[3:0]port - Receive Error G[3:0]_RX_DV Input w/ pull down G[3:0]port - Receive Data Valid AK14, AF13, AH13, AK13, G3_TXD[7:0] AH12, AJ12, AF12, AK12 AF8, AJ8, AK8, AG7, AG8, G2_TXD[7:0] AJ7, AK7, AF7 AG4, AK1, AJ1, AJ2, AH2, G1_TXD[7:0] AH1, AG1, AE5 AA5, AD4, AC2, Y5, AC3, AB2, W5, AB3 G0_TXD[7:0] AB28, Y26, AB29, AB30, NC AA27, AC28, AC29, AA26 AE26, AF28, AG30, AG28, AG27, AH29, AH28, AJ30 AK24, AJ24, AG24, AF24, AH24, AF23, AK23, AJ23 AJ19, AH19, AJ18, AH18, AF20, AK17, AG19, AJ17 AG13, AH8, AK2, AD2 Y27, AG29, AH25, AK19, AJ14, AK9, AJ3, AB5 AB27, AF30, AF25, AH20, AH11, AG5, AG2, AB4 AD28, AH30, AK22, AH17, G[3:0]_TX_EN NC G[3:0]_TX_ER NC G[3:0]_ TXCLK NC Output G[3:0]port - Gigabit Transmit Clock Output w/ pull up G[3:0]port - Transmit Error Output w/ pull up G[3:0]port - Transmit Data Enable Table 7 - Ball- Signal Descriptions (continued) 85 MVTX2801 Ball No(s) Symbol I/O PMA Interface (193) Gigabit Ethernet Access Port (PCS) AJ11, AJ6, AF3,AA4 AD29, AK30, AJ22, AG17, AK15 AF17 GREF_CLK [3:0] NC CM_CLK IND/CM Input w/ pull up Input w/ pull up Input w/ pull up Input w/ pull up Data Sheet Description Gigabit Reference Clock Common Clock shared by port G[3:0] 1: select GREF_CLK[3:0] as clock 0: select CM_CLK as clock for all port G[3:0]port - PMA Receive Data Bit [7:0] AG16, AF16, AG15, AF18, G3_RXD[7:0] AF15, AH15, AJ15, AG14 AG11, AJ10, AF11, AF10, G2_RXD[7:0] AG9, AF9, AH9, AJ9 AF6, AJ5, AF5, AG6, AK4, G1_RXD[7:0] AF4, AK3, AH4 AF1, AC5, AE1, AE2, AE3, AC4, AE4, AD1 G0_RXD[7:0] V26, W29, W30, Y28, W26, NC Y29, W27, Y30 AB26, AE27, AE28, AC27, AE29, AC26, AE30, AD26 AK27, AH27, AF26, AJ27, AH26, AK25, AG26, AJ25 AG22, AG21, AG20, AF22, AK21, AK20, AF21, AJ20 AH16, AH10, AK5, AD5 W28, AD30, AK28, AH22, AF19, AG12, AK6, AF2 V27, AD27, AJ28, AH23, AF14, AK10, AJ4, AD3 AA28, AF29, AJ26, AJ21, AH14, AG10, AH5, AC1 AA29, AF27, AK26, AH21, G[3:0]_RX_D[8] NC G[3:0]_RX_D[9] NC G[3:0]_RXCLK1 NC G[3:0]_RXCLK0 NC Output G[3:0]port - PMA Transmit Data Bit [7:0] Input w/ pull up G[3:0]port - PMA Receive Clock 0 Input w/ pull up G[3:0]port - PMA Receive Clock 1 Input w/ pull up G[3:0]port - PMA Receive Data Bit [9] Input w/ pull down G[3:0]port - PMA Receive Data Bit [8] AK14, AF13, AH13, AK13, G3_TXD[7:0] AH12, AJ12, AF12, AK12 AF8, AJ8, AK8, AG7, AG8, G2_TXD[7:0] AJ7, AK7, AF7 AG4, AK1, AJ1, AJ2, AH2, G1_TXD[7:0] AH1, AG1, AE5 AA5, AD4, AC2, Y5, AC3, AB2, W5, AB3 G0_TXD[7:0] AB28, Y26, AB29, AB30, NC AA27, AC28, AC29, AA26 AE26, AF28, AG30, AG28, AG27, AH29, AH28, AJ30 AK24, AJ24, AG24, AF24, AH24, AF23, AK23, AJ23 AJ19, AH19, AJ18, AH18, AF20, AK17, AG19, AJ17 AG13, AH8, AK2, AD2 Y27, AG29, AH25, AK19, G[3:0]_TXD[8] NC Output w/ pull up G[3:0]port - PMA Transmit Data Bit [8] Table 7 - Ball- Signal Descriptions (continued) 86 Data Sheet Ball No(s) AJ14, AK9, AJ3, AB5 AB27, AF30, AF25, AH20, AH11, AG5, AG2, AB4 AD28, AH30, AK22, AH17, Test Facility (3) U29 T_MODE0 I/O-TS with pull up Symbol G[3:0]_TX_D[9] NC G[3:0]_ TXCLK NC Output I/O Output w/ pull up MVTX2801 Description G[3:0]port - PMA Transmit Data Bit [9] G[3:0]port - PMA Gigabit Transmit Clock Test - Set upon Reset, and provides NAND Tree test output during test mode Use external Pull up for normal operation U28 T_MODE1 I/O-TS with pull up Test - Set upon Reset, and provides NAND Tree test output during test mode. Use external Pull up for normal operation A3 SCAN_EN Input with pull down Enable test mode For normal operation leave it unconnected LED Interface (serial and parallel) R28, T26, R27, T27, U27, T28, T29, T30 T_D[7:0]/ LE_PD[7:0] Output While resetting, T_D[7,0] are in input mode and are used as strapping pins. Internal pull up LE_PD - Parallel Led data [7:0] P27, R26, R30, R29 T_D[11:8]/ LE_PT[3:0] Output While resetting, T_D[11:8] are in input mode and are used as strapping pins. Internal pull up LED_PR[3:0] - Parallel Led port selection [3:0] P26, P30, P29, P28, T_D[15:12]/ LE_PT[7:4] Output While resetting, T_D[15:12] are in input mode and are used as strapping pins. Internal pull up LED_PR[7:4] - No Meaning V29 LE_CLK0/ LE_PT[8] Output LE_CLK0 - LED Serial Interface Output Clock LE_PT[8] - Parallel Led port sel [8] V30 LED_BLINK/ LE_DO/ LE_PT[9] Output While resetting, LED-BLINK is in input mode and is used as strapping pin. 1: No Blink, 0: Blink. Internal pull up. LE_DO - LED Serial Data Output Stream LE_PT[9] - Parallel Led port sel [9] While resetting, LED_PM is in input mode and is used as strapping pin. Internal pull up. 1: Enable parallel interface, 0: enable serial interface. LE_SYNCO# - LED Output Data Stream Envelop V28 LED_PM/ LE_SYNCO# Output with pull up System Clock, Power, and Ground Pins A16 U26 U30 S_CLK S_RST# RESOUT# Input Input - ST Output System Clock at 133 MHz Reset Input Reset PHY Table 7 - Ball- Signal Descriptions (continued) 87 MVTX2801 Ball No(s) B1 B28 AE7, AE9, F10, F21, F22, F9, G25, G6, J25, J6, K25, K6, AA25, AA6, AB25, AB6, AD25, AE10, AE21, AE22 Symbol DEV_CFG[0] DEV_CFG[1] VDD I/O Input w/ pull down Input w/ pull down Power core Not used Not used +2.5 Volt DC Supply Data Sheet Description V14, V15, V16, V17, V18, VSS F16, F24, F25, F6, F7, N13, N14, N15, N16, N17, N18, P13, P14, P15, P16, P17, P18, R13, R14, R15, R16, R17, R18, R25, R6, T13, T14, T15, T16, T17, T18, T25, T6, U13, U14, U15, U16, U17, U18, V13, AD6, AE15, AE16, AE24, AE25, AE6, F15 A1, C28 E5, E25 AE12, AE13, AE14, AE17, AE18, AE19, F12, F13, F14, F17, F18, F19, M25, M6, N25, N6, P25, P6, U25, U6, V25, V6, W25, W6 AVDD AVSS VDD33 Ground Ground Power Ground Power I/O Analog +2.5 Volt DC Supply Analog Ground +3.3 Volt DC Supply Bootstrap Pins (Default= pull up, 1= pull up 0= pull down) AD2 G0_TX_EN Default: PCS Giga0 Mode: G0_TXEN G0_TXER 0 0 1 1 AB5 AK2 G0_TX_ER G1_TX_EN Default: PCS Default: PCS Giga1 Mode: G1_TXEN G1_TXER 0 0 MII 0 1 1 AJ3 AH8 G1_TXER G2_TX_EN Default: PCS Default: PCS Giga2 Mode: G0_TXEN G0_TXER 0 0 MII 0 1 1 AK9 AG13 G2_TX_ER G3_TX_EN Default: PCS Default: PCS Giga3 Mode: G0_TXEN G0_TXER 0 0 MII 0 1 1 AJ14 G3_TX_ER Default: PCS 1 0 1 Invalid GMII PCS 1 0 1 Invalid GMII PCS 1 0 1 Invalid GMII PCS 0 1 0 1 MII Invalid GMII PCS Table 7 - Ball- Signal Descriptions (continued) 88 Data Sheet Ball No(s) Symbol I/O After reset T_d[15:0] are used by the LED interface T30 T29 T_d[0] T_d[1] 1 1 MVTX2801 Description Giga link active status 0 - active low 1 active high Power saving 0 - No power saving 1 - Power saving Stop MAC clock if no MAC activity. Reserved - Must be pulled-down Hot plug port module detection enable 0 - module detection enable 1 - module detection disable Reserved - Must be pulled-down SRAM memory size 0 - 512K SRAM 1 - 256K SRAM Reserved T28 U27 T_d[2] T_d[3] Must be pulled-down 1 T27 R27 T_d[4] T_d[5] Must be pulled-down 1 T26 R28 T_d[6] T_d[7] 1 FDB memory depth 1- one memory layer 0 - two memory layers FDB memory size 11 - 2M per bank = 4M total 10 - 1M per bank = 2M total 0x - 512K per bank = 1M total EEPROM installed 0 - EEPROM is installed 1 - EEPROM is not installed MCT Aging enable 0 - MCT aging disable 1 - MCT aging enable FCB handle aging enable 0 - FCB handle aging disable 1 - FCB handle aging enable Timeout reset enable 0 - timeout reset disable 1 - timeout reset enable Issue reset if any state machine did not go back to idle for 5sec. Reserved W4, E21 La_a[20], Lb_a[20] 11 R29 T_d[8] 1 R30 T_d[9] 1 R26 T_d[10] 1 P27 T_d[11] 1 P28, 29, 30 P26 T_d[14:12] T_d[15] 1 External RAM test 0 - Perform the infinite loop of ZBT RAM BIST. Debug test only 1 - Regular operation. ZBT RAM la_clk turning 3'b000 - control by reg. LCLKCR[2:0] 3'b001 - delay by method # 0 3'b010 - delay by method # 1 3'b011 - delay by method # 2 3'b100 - delay by method # 3 3'b101 - delay by method # 4 3'b110 - delay by method # 5 3'b111 - delay by method # 6 - USE THIS METHOD N30, N29, N28 P_d[2:0] 111 M30, M29, M28 P_d[5:3] 111 No Use Table 7 - Ball- Signal Descriptions (continued) 89 MVTX2801 Ball No(s) L29, L28, N26 P_d[8:6] Symbol 111 I/O Data Sheet Description SBRAM b_clk turning3'b000 - control by BCLKCR[2:0] 3'b001 - delay by method # 0 3'b010 - delay by method # 1 3'b011 - delay by method # 2 3'b100 - delay by method # 3 3'b101 - delay by method # 4 3'b110 - delay by method # 5 3'b111 - delay by method # 6 - USE THIS METHOD Table 7 - Ball- Signal Descriptions (continued) Notes: #= Input = In-ST = Output = Active low signal Input signal Input signal with Schmitt-Trigger Output signal (Tri-State driver) Out-OD= I/O-TS = I/O-OD = Output signal with Open-Drain driver Input & Output signal with Tri-State driver Input & Output signal with Open-Drain driver 90 Data Sheet 11.4 Ball No. A1 B1 B2 C2 C1 D1 C3 E4 D2 E3 E2 E1 D3 F1 F2 F3 F4 F5 G1 G2 G5 G4 G3 H1 H2 H3 J1 H5 J2 J3 J4 K1 H4 K2 MVTX2801 Signal Name AVDD DEV_CFG[0] LA_D[0] LA_CLK LA_D[1] LA_D[2] LA_D[3] LA_D[4] LA_D[5] LA_D[6] LA_D[7] LA_D[8] LA_D[9] LA_D[10] LA_D[11] LA_D[12] LA_D[13] LA_D[14] LA_D[15] LA_D[16] LA_D[17] LA_D[18] LA_D[19] LA_D[20] LA_D[21] LA_D[22] LA_D[23] LA_D[24] LA_D[25] LA_D[26] LA_D[27] LA_D[28] LA_D[29] LA_D[30] Ball No. M1 M2 M3 K4 N1 P5 N2 L5 N3 P1 P2 P3 L4 R5 M5 R1 R2 R3 R4 M4 T4 T3 N5 T2 T1 U4 U3 N4 U2 U1 V3 P4 V2 V1 Signal Name LA_D[34] LA_D[35] LA_D[36] LA_D[37] LA_D[38] LA_D[39] LA_D[40] LA_D[41] LA_D[42] LA_D[43] LA_D[44] LA_D[45] LA_D[46] LA_D[47] LA_D[48] LA_D[49] LA_D[50] LA_D[51] LA_D[52] LA_D[53] LA_D[54] LA_D[55] LA_D[56] LA_D[57] LA_D[58] LA_D[59] LA_D[60] LA_D[61] LA_D[62] LA_D[63] LA_A[3] LA_A[4] LA_A[5] LA_A[6] Ball No. Y2 V4 Y1 AA3 AA2 V5 AA1 W4 Y4 AA4 AB4 AB3 W5 AB2 AB1 AC3 Y5 AC2 AC1 AD3 AD4 AA5 AD2 AB5 AD1 AE4 AC4 AE3 AE2 AE1 AC5 AF1 AD5 AF2 Signal Name LA_A[13] LA_A[14] LA_A[15] LA_A[16] LA_A[17] LA_A[18] LA_A[19] LA_A[20] G0_CRS/LINK GREF_CLK[0] G0_TXCLK G0_TXD[0] G0_TXD[1] G0_TXD[2] MII_TX_CLK[0] G0_TXD[3] G0_TXD[4] G0_TXD[5] G0_RXCLK G0_COL G0_TXD[6] G0_TXD[7] G0_TX_EN G0_TX_ER G0_RXD[0] G0_RXD[1] G0_RXD[2] G0_RXD[3] G0_RXD[4] G0_RXD[5] G0_RXD[6] G0_RXD[7] G0_RX_DV G0_RX_ER Ball Signal Name Table 8 - Ball Signal Name 91 MVTX2801 Ball No. J5 K3 L1 L2 L3 K5 AH2 AJ2 AJ1 AK1 AG4 AK2 AH3 AJ3 AH4 AK3 AF4 AK4 AH5 AJ4 AG6 AF5 AJ5 AF6 AK5 AK6 AJ6 AG5 AH6 AF7 AK7 AJ7 AG8 AG7 AH7 Signal Name LA_D[31] LA_CS0# LA_CS1# LA_RW# LA_D[32] LA_D[33] G1_TXD[3] G1_TXD[4] G1_TXD[5] G1_TXD[6] G1_TXD[7] G1_TX_EN MII_TX_CLK[1] G1_TX_ER G1_RXD[0] G1_RXD[1] G1_RXD[2] G1_RXD[3] G1_RXCLK G1_COL G1_RXD[4] G1_RXD[5] G1_RXD[6] G1_RXD[7] G1_RX_DV G1_RX_ER GREF_CLK[2] G2_TXCLK G2_CRS/LINK G2_TXD[0] G2_TXD[1] G2_TXD[2] G2_TXD[3] G2_TXD[4] MII_TX_CLK[2] Ball No. T5 W3 W2 W1 U5 Y3 AG10 AK10 AJ10 AG11 AH10 AG12 AK11 AJ11 AH11 AK12 AF12 AJ12 AH12 AK13 AJ13 AH13 AF13 AK14 AG13 AJ14 AH14 AF14 AG14 AK15 AF17 AJ15 AH15 AF15 AF18 Signal Name LA_A[7] LA_A[8] LA_A[9] LA_A[10] LA_A[11] LA_A[12] G2_RXCLK G2_COL G2_RXD[6] G2_RXD[7] G2_RX_DV G2_RX_ER G3_CRS/LINK GREF_CLK[3] G3_TXCLK G3_TXD[0] G3_TXD[1] G3_TXD[2] G3_TXD[3] G3_TXD[4] MII_TX_CLK[3] G3_TXD[5] G3_TXD[6] G3_TXD[7] G3_TX_EN G3_TX_ER G3_RXCLK G3_COL G3_RXD[0] CM_CLK IND_CM G3_RXD[1] G3_RXD[2] G3_RXD[3] G3_RXD[4] Ball No. AF3 AG2 AG3 AE5 AG1 AH1 AG19 AK17 AF20 AH18 AJ18 AK18 AH19 AJ19 AK19 AH20 AJ20 AF21 AK20 AH21 AJ21 AK21 AF22 AG20 AG21 AG22 AH22 AJ22 AK22 AH23 AG23 AJ23 AK23 AF23 AH24 Data Sheet Signal Name GREF_CLK[1] G1_TXCLK G1_CRS/LINK G1_TXD[0] G1_TXD[1] G1_TXD[2] NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Table 8 - Ball Signal Name (continued) 92 Data Sheet Ball No. AK8 AJ8 AF8 AH8 AK9 AJ9 AH9 AF9 AG9 AF10 AF11 AJ26 AH26 AJ27 AF26 AH27 AK27 AK28 AJ28 AJ29 AK29 AK30 AJ30 AH28 AH29 AG27 AG28 AH30 AG30 AF28 AE26 AG29 AF27 AF29 AF30 Signal Name G2_TXD[5] G2_TXD[6] G2_TXD[7] G2_TX_EN G2_TX_ER G2_RXD[0] G2_RXD[1] G2_RXD[2] G2_RXD[3] G2_RXD[4] G2_RXD[5] NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Ball No. AG15 AF16 AG16 AH16 AF19 AJ16 AG18 AK16 AG17 AH17 AJ17 AA27 AB30 AB29 Y26 AB28 Y27 AB27 AA30 AA29 AA28 Y30 W27 Y29 W26 Y28 W30 W29 V26 W28 V27 V30 V29 V28 U26 Signal Name G3_RXD[5] G3_RXD[6] G3_RXD[7] G3_RX_DV G3_RX_ER M_MDC M_MDIO NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC LE_DO LE_CLK0 LE_SYNCO# S_RST# Ball No. AF24 AG24 AJ24 AK24 AG25 AH25 AF25 AJ25 AG26 AK25 AK26 P29 P30 P26 N28 N29 N30 M28 M29 M30 N26 L28 L29 N27 L30 K28 K29 K30 L27 K27 M26 J27 J28 J29 J30 NC NC NC NC NC NC NC NC NC NC NC MVTX2801 Signal Name T_D[13] T_D[14] T_D[15] P_D[0] P_D[1] P_D[2] P_D[3] P_D[4] P_D[5] P_D[6] P_D[7] P_D[8] P_D[9] P_D[10] P_D[11] P_D[12] P_D[13] P_D[14] P_D[15] P_A[0] P_A[1] P_A[2] P_WE# P_RD# Table 8 - Ball Signal Name (continued) 93 MVTX2801 Ball No. AD26 AE30 AC26 AE29 AC27 AE28 AE27 AB26 AD30 AD29 AD27 AD28 AC30 AA26 AC29 AC28 E30 H26 E29 E26 D29 E28 G26 D30 C30 E27 C29 D28 B30 F26 D26 A30 A29 B29 E25 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC B_D[14] B_D[15] B_D[16] B_D[17] B_D[18] B_D[19] B_D[20] B_D[21] B_D[22] B_D[23] B_CLK B_D[24] B_D[25] NC1 NC2 NC3 NC4 NC5 AGND Signal Name Ball No. U30 U29 U28 T30 T29 T28 U27 T27 R27 T26 R28 R29 R30 R26 P27 P28 A23 B23 C23 E22 A22 B22 C22 E21 D22 D20 E20 D21 A21 D19 B21 C21 A20 B20 E19 Signal Name RESOUT# T_MODE[0] T_MODE[1] T_D[0] T_D[1] T_D[2] T_D[3] T_D[4] T_D[5] T_D[6] T_D[7] T_D[8] T_D[9] T_D[10] T_D[11] T_D[12] B_A[12] B_A[13] B_A[14] B_A[15] B_A[16] B_A[17] B_A[18] LB_A[20] NC NC NC NC NC NC NC NC NC NC NC Ball No. L26 H28 M27 H29 H30 G28 G27 K26 G29 G30 H27 F27 F28 F29 F30 J26 E14 C15 B15 E13 A15 D14 C14 D13 B14 A14 C13 E12 B13 A13 D12 C12 B12 A12 C11 P_CS# P_INT# B_D[0] B_D[1] B_D[2] B_D[3] B_D[4] B_D[5] B_D[6] B_D[7] B_D[8] B_D[9] B_D[10] B_D[11] B_D[12] B_D[13] NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Data Sheet Signal Name Table 8 - Ball Signal Name (continued) 94 Data Sheet Ball No. B28 C28 A28 A27 C27 D27 B27 E24 D25 B26 A26 A25 B25 C26 C25 E23 A24 B24 D23 D24 C24 B7 E8 A7 D6 C6 E6 B6 A6 A5 B5 C5 B4 D5 A4 Signal Name DEV_CFG[1] AVDD B_D[26] B_D[27] B_D[28] B_D[29] B_D[30] B_D[31] B_ADSC# B_WE# B_OE# B_A[2] B_A[3] B_A[4] B_A[5] B_A[6] B_A[7] B_A[8] B_A[9] B_A[10] B_A[11] NC NC NC NC NC NC NC NC NC NC NC NC NC NC Ball No. C20 A19 B19 E18 C19 A18 D18 B18 C18 A17 E17 B17 C17 E16 D17 A16 B16 E15 C16 D16 D15 P15 P16 P17 P18 R13 R14 R15 R16 R17 R18 R25 R6 T13 T14 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC S_CLK NC NC NC NC NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Signal Name Ball No. E11 B11 A11 E10 C10 B10 E9 A10 D11 D10 D8 D9 C9 B9 A9 C8 B8 A8 C7 E7 D7 AE7 AE9 F10 F21 F22 F9 G25 G6 J25 J6 K25 K6 AE12 AE13 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC MVTX2801 Signal Name VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VD33 VD33 Table 8 - Ball Signal Name (continued) 95 MVTX2801 Ball No. A3 E5 C4 B3 D4 A2 AD6 AE15 AE16 AE24 AE25 AE6 F15 F16 F24 F25 F6 F7 N13 N14 N15 N16 N17 N18 P13 P14 Signal Name SCAN_EN AGND NC6 NC7 NC8 NC9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball No. T15 T16 T17 T18 T25 T6 U13 U14 U15 U16 U17 U18 V13 V14 V15 V16 V17 V18 AA25 AA6 AB25 AB6 AD25 AE10 AE21 AE22 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD Signal Name Ball No. AE14 AE17 AE18 AE19 F12 F13 F14 F17 F18 F19 M25 M6 N25 N6 P25 P6 U25 U6 V25 V6 W25 W6 VD33 VD33 VD33 VD33 VD33 VD33 VD33 VD33 VD33 VD33 VD33 VD33 VD33 VD33 VD33 VD33 VD33 VD33 VD33 VD33 VD33 VD33 Data Sheet Signal Name Table 8 - Ball Signal Name (continued) 96 Data Sheet 11.5 11.5.1 AC/DC Timing Absolute Maximum Ratings -65oC to +150oC -40oC to +85oC +3.0 V to +3.6 V +2.38 V to +2.75 V MVTX2801 Storage Temperature Operating Temperature Supply Voltage VDD33 with Respect to VSS Supply Voltage VDD with Respect to VSS Voltage on Input Pins -0.5 V to (VDD33 + 3.3 V) Caution: Stress above those listed may damage the device. Exposure to the Absolute Maximum Ratings for extended periods may affect device reliability. Functionality at or above these limits is not implied. 11.5.2 DC Electrical Characteristics TAMBIENT = -40oC to +85oC VDD33 = 3.0 V to 3.6 V (3.3v +/- 10%) VDD = 2.5V +10% - 5% 11.5.3 Recommended Operation Conditions Preliminary Symbol fosc IDD1 IDD2 VOH VOL VIH-TTL VIL-TTL IIH-5VT CIN COUT CI/O Parameter Description Min Frequency of Operation Supply Current - @ 133 MHz (VDD33 = 3.3V) Supply Current - @ 133 MHz (VDD = 2.5V) Output High Voltage (CMOS) Output Low Voltage (CMOS) Input High Voltage (TTL 5V tolerant) Input Low Voltage (TTL 5V tolerant) Input Leakage Current (0.1 V < VIN < VDD33) Input Capacitance Output Capacitance I/O Capacitance Table 9 - Recommended Operation Conditions VDD33 x 70% 680 1300 VDD33 - 0.5 0.5 VDD33 + 2.0 VDD33 x 30% 10 5 5 7 Type 133 850 1500 Max Unit MHz mA mA V V V V A pF pF pF 97 MVTX2801 11.6 11.6.1 Local Frame Buffer ZBT SRAM Memory Interface Local ZBT SRAM Memory Interface A Data Sheet LA_CLK L1 L2 LA_D[63:0] Figure 8 - Local Memory Interface - Input setup and hold timing LA_CLK L3-max L3-min LA_D[63:0] L4-max L4-min LA_A[20:3] L6-max L6-min LA_CS[1,0]# L9-max L9-min LA_RW# Figure 9 - Local Memory Interface - Output valid delay timing (SCLK= 133MHz) Symbol L1 L2 L3 L4 L6 L9 Parameter LA_D[63:0] input set-up time LA_D[63:0] input hold time LA_D[63:0] output valid delay LA_A[20:3] output valid delay LA_CS[1:0]# output valid delay LA_WE# output valid delay Min (ns) 2.5 1 3 3 3 3 5 5 5 5 CL = 25pf CL = 30pf CL = 30pf CL = 25pf Max (ns) Note: Table 10 - AC Characteristics - Local frame buffer ZBT-SRAM Memory Interface A 98 Data Sheet 11.7 11.7.1 Local Switch Database SBRAM Memory Interface Local SBRAM Memory Interface MVTX2801 B_CLK L1 L2 B_D[31:0] Figure 10 - Local Memory Interface - Input setup and hold timing B_CLK L3-max L3-min B_D[31:0] L4-max L4-min B_A[18:2] L6-max L6-min B_ADSC# L10-max L10-min B_WE# L11-max L11-min B_OE# Figure 11 - Local Memory Interface - Output valid delay timing (SCLK= 133MHz) Symbol L1 L2 L3 L4 L6 L10 L11 Parameter B_D[31:0] input set-up time B_D[31:0] input hold time B_D[31:0] output valid delay B_A[18:2] output valid delay B_ADSC# output valid delay B_WE# output valid delay B_OE# output valid delay Min (ns) 2.5 1 3 3 3 3 3 5 5 5 5 4 CL = 25pf CL = 30pf CL = 30pf CL = 25pf CL = 25pf Max (ns) Note: Table 11 - AC Characteristics - Local Switch Database SBRAM Memory Interface 99 MVTX2801 11.8 11.8.1 AC Characteristics Media Independent Interface MII_TXCLK[3:0] M6-max M6-min Data Sheet G[3:0]_TXEN M7-max M7-min G[3:0] _TXD[3:0] Figure 12 - AC Characteristics - Media Independent Interface G[3:0]_RXCLK M2 G[3:0]_RXD[3:0] M3 G[3:0]_CRS_DV M4 M5 Figure 13 - AC Characteristics - Media Independent Interface (MII_TXCLK & G_RXCLK = 25MHz) Symbol M2 M3 M4 M5 M6 M7 Parameter G[3:0]_RXD[3:0] Input Setup Time G[3:0]_RXD[3:0] Input Hold Time G[3:0]_CRS_DV Input Setup Time G[3:0]_CRS_DV Input Hold Time G[3:0]_TXEN Output Delay Time G[3:0]_TXD[3:0] Output Delay Time Min (ns) 4 1 4 1 3 3 11 11 CL = 20 pF CL = 20 pF Max (ns) Note: Table 12 - AC Characteristics - Media Independent Interface 100 Data Sheet 11.8.2 Gigabit Media Independent Interface G[3:0]_TXCLK G12-max G12-min MVTX2801 G[3:0]_TXD[7:0] G13-max G13-min G[3:0]_TX_EN G14-max G14-min G[3:0]_TX_ER Figure 14 - AC Characteristics- GMII G[3:0]_RXCLK G1 G2 G[3:0]_RXD[7:0] G3 G4 G[3:0]_RX_DV G5 G6 G[3:0]_RX_ER G7 G8 G[3:0]_RX_CRS Figure 15 - AC Characteristics - Gigabit Media Independent Interface 101 MVTX2801 (G_RCLK & G_REFCLK = 125MHz) Symbol G1 G2 G3 G4 G5 G6 G7 G8 G12 G13 G14 Parameter G[3:0]_RXD[7:0] Input Setup Times G[3:0]_RXD[7:0] Input Hold Times G[3:0]_RX_DV Input Setup Times G[3:0]_RX_DV Input Hold Times G[3:0]_RX_ER Input Setup Times G[3:0]_RX_ER Input Hold Times G[3:0]_CRS Input Setup Times G[3:0]_CRS Input Hold Times G[3:0]_TXD[7:0] Output Delay Times G[3:0]_TX_EN Output Delay Times G[3:0]_TX_ER Output Delay Times 2 1 2 1 2 1 2 1 1 1 1 5 5 5 Min (ns) Max (ns) Data Sheet Note: CL = 20pf CL = 20pf CL = 20pf Table 13 - AC Characteristics - Gigabit Media Independent Interface 11.8.3 PCS Interface G[3:0]_TXCLK G30-max G30-min G[3:0]_TXD[9:0] Figure 16 - AC Characteristics - PCS Interface G[3:0]_RXCLK1 G[3:0]_RXCLK G[3:0]_RXD[9:0] G[3:0]_RX_CRS Figure 17 - AC Characteristics - PCS Interface 102 Data Sheet (G_RCLK & G_REFCLK = 125MHz) Symbol G21 G22 G23 G24 G25 G26 G30 Parameter G[3:0]_RXD[9:0] Input Setup Times ref to G_RXCLK G[3:0]_RXD[9:0] Input Hold Times ref to G_RXCLK G[3:0]_RXD[9:0] Input Setup Times ref to G_RXCLK1 G[3:0]_RXD[9:0] Input Hold Times ref to G_RXCLK1 G[3:0]_CRS Input Setup Times G[3:0]_CRS Input Hold Times G[3:0]_TXD[9:0] Output Delay Times Min (ns) 2 1 2 1 2 1 1 5 Max (ns) MVTX2801 Note: CL = 20pf Table 14 - AC Characteristics - PCS Interface 11.8.4 LED Interface LED_CLK LE5-max LE5-min LED_SYN LE6-max LE6-min LED_BIT Figure 18 - AC Characteristics - LED Interface Variable FREQ. Symbol LE5 LE6 Parameter LED_SYN Output Valid Delay LED_BIT Output Valid Delay Min (ns) 1 1 Max (ns) 7 7 Note: CL = 30pf CL = 30pf Table 15 - AC Characteristics - LED Interface 103 MVTX2801 11.8.5 MDIO Input Setup and Hold Timing Data Sheet MDC D1 D2 MDIO Figure 19 - MDIO Input Setup and Hold Timing MDC D3-max D3-min MDIO Figure 20 - MDIO Output Delay Timing 1MHz Symbol D1 D2 D3 Parameter MDIO input setup time MDIO input hold time MDIO output delay time Min (ns) 10 2 1 20 CL = 50pf Max (ns) Note: Table 16 - MDIO Timing 11.8.6 I2C Input Setup Timing SCL S1 S2 SDA Figure 21 - I2C Input Setup Timing 104 Data Sheet SCL S3-max S3-min MVTX2801 SDA Figure 22 - I2C Output Delay Timing 500KHz Symbol S1 S2 S3 Parameter SDA input setup time SDA input hold time SDA output delay time Min (ns) 20 1 1 20 CL = 30pf Max (ns) Note: Open Drain Output. Low to High transistor is controlled by external pullup resistor. Table 17 - I2C Timing 11.8.7 Serial Interface Setup Timing STROBE D1 D2 D4 D1 D2 D5 PS_DI Figure 23 - Serial Interface Setup Timing STROBE D3-max D3-min PS_DO Figure 24 - Serial Interface Output Delay Timing 105 MVTX2801 (SCLK =133 MHz) Symbol D1 D2 D3 D4 D5 Parameter PS_DI setup time PS_DI hold time PS_DO output delay time Strobe low time Strobe high time 20 10 1 5s 5s Table 18 - Serial Interface Timing 50 Min (ns) Max (ns) Data Sheet Note: CL = 100pf 12.0 12.1 Mechanical Data Packaging Information 596 PIN BGA Packaging Diagram. 40 x 40 mm 106 E1 E MIN MAX A 2.20 2.46 A1 0.50 0.70 A2 1.17 REF 40.20 D 39.80 D1 34.50 REF E 40.20 39.80 E1 34.50 REF b 0.60 0.90 e 1.27 596 Conforms to JEDEC MS - 034 e D1 D A2 NOTE: b A1 A 1. CONTROLLING DIMENSIONS ARE IN MM 2. DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER 3. SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 4. N IS THE NUMBER OF SOLDER BALLS 5. NOT TO SCALE. 6. SUBSTRATE THICKNESS IS 0.56 MM Package Code ISSUE ACN DATE APPRD. Previous package codes: For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002, Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE |
Price & Availability of MVTX2801
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |